From fc29db1214736d6ed84d60707db28de346af3feb Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 3 Dec 2012 22:51:04 +0000 Subject: [PATCH] Use the new getRegAllocationHints() hook from AllocationOrder. This simplifies the hinting code quite a bit while making the targets easier to write at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169173 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/AllocationOrder.cpp | 81 ++++++++++++++------------------- lib/CodeGen/AllocationOrder.h | 47 +++++++------------ 2 files changed, 49 insertions(+), 79 deletions(-) diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp index bad4912e722..0f32b66f413 100644 --- a/lib/CodeGen/AllocationOrder.cpp +++ b/lib/CodeGen/AllocationOrder.cpp @@ -14,10 +14,15 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "regalloc" #include "AllocationOrder.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/VirtRegMap.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -25,56 +30,36 @@ using namespace llvm; AllocationOrder::AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo) - : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { - const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); - std::pair HintPair = - VRM.getRegInfo().getRegAllocationHint(VirtReg); - const MachineRegisterInfo &MRI = VRM.getRegInfo(); + : Pos(0) { + const MachineFunction &MF = VRM.getMachineFunction(); + const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); + Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); + TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); - // HintPair.second is a register, phys or virt. - Hint = HintPair.second; - - // Translate to physreg, or 0 if not assigned yet. - if (TargetRegisterInfo::isVirtualRegister(Hint)) - Hint = VRM.getPhys(Hint); - - // The first hint pair component indicates a target-specific hint. - if (HintPair.first) { - const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); - // The remaining allocation order may depend on the hint. - ArrayRef Order = - TRI.getRawAllocationOrder(RC, HintPair.first, Hint, - VRM.getMachineFunction()); - if (Order.empty()) - return; - - // Copy the allocation order with reserved registers removed. - OwnedBegin = true; - MCPhysReg *P = new MCPhysReg[Order.size()]; - Begin = P; - for (unsigned i = 0; i != Order.size(); ++i) - if (!MRI.isReserved(Order[i])) - *P++ = Order[i]; - End = P; - - // Target-dependent hints require resolution. - Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint, - VRM.getMachineFunction()); - } else { - // If there is no hint or just a normal hint, use the cached allocation - // order from RegisterClassInfo. - ArrayRef O = RCI.getOrder(RC); - Begin = O.begin(); - End = O.end(); - } + DEBUG({ + if (!Hints.empty()) { + dbgs() << "hints:"; + for (unsigned I = 0, E = Hints.size(); I != E; ++I) + dbgs() << ' ' << PrintReg(Hints[I], TRI); + dbgs() << '\n'; + } + }); +} - // The hint must be a valid physreg for allocation. - if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || - !RC->contains(Hint) || MRI.isReserved(Hint))) - Hint = 0; +bool AllocationOrder::isHint(unsigned PhysReg) const { + return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end(); } -AllocationOrder::~AllocationOrder() { - if (OwnedBegin) - delete [] Begin; +unsigned AllocationOrder::next() { + if (Pos < Hints.size()) + return Hints[Pos++]; + ArrayRef::iterator I = Order.begin() + (Pos - Hints.size()); + ArrayRef::iterator E = Order.end(); + while (I != E) { + unsigned Reg = *I++; + ++Pos; + if (!isHint(Reg)) + return Reg; + } + return 0; } diff --git a/lib/CodeGen/AllocationOrder.h b/lib/CodeGen/AllocationOrder.h index 862a3ee1923..3d3686bf1a7 100644 --- a/lib/CodeGen/AllocationOrder.h +++ b/lib/CodeGen/AllocationOrder.h @@ -18,6 +18,7 @@ #define LLVM_CODEGEN_ALLOCATIONORDER_H #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/ADT/ArrayRef.h" namespace llvm { @@ -25,15 +26,12 @@ class RegisterClassInfo; class VirtRegMap; class AllocationOrder { - const MCPhysReg *Begin; - const MCPhysReg *End; - const MCPhysReg *Pos; - const RegisterClassInfo &RCI; - unsigned Hint; - bool OwnedBegin; -public: + SmallVector Hints; + ArrayRef Order; + unsigned Pos; - /// AllocationOrder - Create a new AllocationOrder for VirtReg. +public: + /// Create a new AllocationOrder for VirtReg. /// @param VirtReg Virtual register to allocate for. /// @param VRM Virtual register map for function. /// @param RegClassInfo Information about reserved and allocatable registers. @@ -41,32 +39,19 @@ public: const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo); - ~AllocationOrder(); + /// Return the next physical register in the allocation order, or 0. + /// It is safe to call next() again after it returned 0, it will keep + /// returning 0 until rewind() is called. + unsigned next(); - /// next - Return the next physical register in the allocation order, or 0. - /// It is safe to call next again after it returned 0. - /// It will keep returning 0 until rewind() is called. - unsigned next() { - // First take the hint. - if (!Pos) { - Pos = Begin; - if (Hint) - return Hint; - } - // Then look at the order from TRI. - while (Pos != End) { - unsigned Reg = *Pos++; - if (Reg != Hint) - return Reg; - } - return 0; - } - - /// rewind - Start over from the beginning. + /// Start over from the beginning. void rewind() { Pos = 0; } - /// isHint - Return true if PhysReg is a preferred register. - bool isHint(unsigned PhysReg) const { return PhysReg == Hint; } + /// Return true if the last register returned from next() was a preferred register. + bool isHint() const { return Pos <= Hints.size(); } + + /// Return true if PhysReg is a preferred register. + bool isHint(unsigned PhysReg) const; }; } // end namespace llvm -- 2.34.1