From fdb1767c626b3a58a5aeb7aad4796dff83effaeb Mon Sep 17 00:00:00 2001 From: WeiYong Bi Date: Thu, 3 Aug 2017 09:56:05 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3399: Correct DPHY PLL clock clk_24m --> Gate --> clk_mipidphy_ref --> Gate --> clk_dphy_pll Change-Id: Icb5283c0854a475a5f2fc436e7d4448393b5ac95 Signed-off-by: WeiYong Bi --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 80175f35cb97..6d11ce20bfdc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1914,7 +1914,7 @@ compatible = "rockchip,rk3399-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = ; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; resets = <&cru SRST_P_MIPI_DSI0>; -- 2.34.1