From fdc7c7ad10aded7dbd3bb2ce85f194efa5d08c06 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 30 Aug 2015 22:12:50 +0000 Subject: [PATCH] [PowerPC] Fixup SELECT_CC (and SETCC) patterns with i1 comparison operands There were really two problems here. The first was that we had the truth tables for signed i1 comparisons backward. I imagine these are not very common, but if you have: setcc i1 x, y, LT this has the '0 1' and the '1 0' results flipped compared to: setcc i1 x, y, ULT because, in the signed case, '1 0' is really '-1 0', and the answer is not the same as in the unsigned case. The second problem was that we did not have patterns (at all) for the unsigned comparisons select_cc nodes for i1 comparison operands. This was the specific cause of PR24552. These had to be added (and a missing Altivec promotion added as well) to make sure these function for all types. I've added a bunch more test cases for these patterns, and there are a few FIXMEs in the test case regarding code-quality. Fixes PR24552. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246400 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 2 + lib/Target/PowerPC/PPCInstrInfo.td | 120 +- lib/Target/PowerPC/PPCInstrQPX.td | 24 + lib/Target/PowerPC/PPCInstrVSX.td | 27 +- test/CodeGen/PowerPC/select-i1-vs-i1.ll | 1685 +++++++++++++++++++++++ 5 files changed, 1853 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/PowerPC/select-i1-vs-i1.ll diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 72d1d19d0f3..2480c65b9ed 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -431,6 +431,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); setOperationAction(ISD::SELECT, VT, Promote); AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); + setOperationAction(ISD::SELECT_CC, VT, Promote); + AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); setOperationAction(ISD::STORE, VT, Promote); AddPromotedToType (ISD::STORE, VT, MVT::v4i32); diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index b50124db1ea..24fd9bd5c1f 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -2835,24 +2835,84 @@ def : Pat<(i64 (anyext i1:$in)), (SELECT_I8 $in, (LI8 1), (LI8 0))>; // match setcc on i1 variables. +// CRANDC is: +// 1 1 : F +// 1 0 : T +// 0 1 : F +// 0 0 : F +// +// LT is: +// -1 -1 : F +// -1 0 : T +// 0 -1 : F +// 0 0 : F +// +// ULT is: +// 1 1 : F +// 1 0 : F +// 0 1 : T +// 0 0 : F def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), - (CRANDC $s2, $s1)>; + (CRANDC $s1, $s2)>; def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), (CRANDC $s2, $s1)>; +// CRORC is: +// 1 1 : T +// 1 0 : T +// 0 1 : F +// 0 0 : T +// +// LE is: +// -1 -1 : T +// -1 0 : T +// 0 -1 : F +// 0 0 : T +// +// ULE is: +// 1 1 : T +// 1 0 : F +// 0 1 : T +// 0 0 : T def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), - (CRORC $s2, $s1)>; + (CRORC $s1, $s2)>; def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), (CRORC $s2, $s1)>; + def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), (CREQV $s1, $s2)>; + +// GE is: +// -1 -1 : T +// -1 0 : F +// 0 -1 : T +// 0 0 : T +// +// UGE is: +// 1 1 : T +// 1 0 : T +// 0 1 : F +// 0 0 : T def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), - (CRORC $s1, $s2)>; + (CRORC $s2, $s1)>; def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), (CRORC $s1, $s2)>; + +// GT is: +// -1 -1 : F +// -1 0 : F +// 0 -1 : T +// 0 0 : F +// +// UGT is: +// 1 1 : F +// 1 0 : T +// 0 1 : F +// 0 0 : F def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), - (CRANDC $s1, $s2)>; + (CRANDC $s2, $s1)>; def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), (CRANDC $s1, $s2)>; + def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), (CRXOR $s1, $s2)>; @@ -3203,18 +3263,30 @@ def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), // select (lhs == rhs), tval, fval is: // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), + (CROR (CRAND (CRANDC $lhs, $rhs), $tval), + (CRAND (CRORC $rhs, $lhs), $fval))>; +def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), (CROR (CRAND (CRANDC $rhs, $lhs), $tval), (CRAND (CRORC $lhs, $rhs), $fval))>; def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), + (CROR (CRAND (CRORC $lhs, $rhs), $tval), + (CRAND (CRANDC $rhs, $lhs), $fval))>; +def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), (CROR (CRAND (CRORC $rhs, $lhs), $tval), (CRAND (CRANDC $lhs, $rhs), $fval))>; def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), (CROR (CRAND (CREQV $lhs, $rhs), $tval), (CRAND (CRXOR $lhs, $rhs), $fval))>; def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), + (CROR (CRAND (CRORC $rhs, $lhs), $tval), + (CRAND (CRANDC $lhs, $rhs), $fval))>; +def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), (CROR (CRAND (CRORC $lhs, $rhs), $tval), (CRAND (CRANDC $rhs, $lhs), $fval))>; def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), + (CROR (CRAND (CRANDC $rhs, $lhs), $tval), + (CRAND (CRORC $lhs, $rhs), $fval))>; +def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), (CROR (CRAND (CRANDC $lhs, $rhs), $tval), (CRAND (CRORC $rhs, $lhs), $fval))>; def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), @@ -3223,66 +3295,106 @@ def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), // match selectcc on i1 variables with non-i1 output. def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), + (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), + (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), + (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), + (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), + (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), + (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), + (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), + (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), + (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), + (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), + (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), + (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), + (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), + (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), + (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), + (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), + (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), + (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), + (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), + (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; diff --git a/lib/Target/PowerPC/PPCInstrQPX.td b/lib/Target/PowerPC/PPCInstrQPX.td index 5c66b42690c..0a044c5c6ea 100644 --- a/lib/Target/PowerPC/PPCInstrQPX.td +++ b/lib/Target/PowerPC/PPCInstrQPX.td @@ -1115,40 +1115,64 @@ def : Pat<(v4f64 (PPCqbflt v4i1:$src)), (COPY_TO_REGCLASS $src, QFRC)>; def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETLT)), + (SELECT_QFRC (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)), (SELECT_QFRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETLE)), + (SELECT_QFRC (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULE)), (SELECT_QFRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETEQ)), (SELECT_QFRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETGE)), + (SELECT_QFRC (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)), (SELECT_QFRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETGT)), + (SELECT_QFRC (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGT)), (SELECT_QFRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETNE)), (SELECT_QFRC (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETLT)), + (SELECT_QSRC (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)), (SELECT_QSRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETLE)), + (SELECT_QSRC (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULE)), (SELECT_QSRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETEQ)), (SELECT_QSRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETGE)), + (SELECT_QSRC (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)), (SELECT_QSRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETGT)), + (SELECT_QSRC (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGT)), (SELECT_QSRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETNE)), (SELECT_QSRC (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETLT)), + (SELECT_QBRC (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)), (SELECT_QBRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETLE)), + (SELECT_QBRC (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULE)), (SELECT_QBRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETEQ)), (SELECT_QBRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETGE)), + (SELECT_QBRC (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)), (SELECT_QBRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETGT)), + (SELECT_QBRC (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGT)), (SELECT_QBRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETNE)), (SELECT_QBRC (CRXOR $lhs, $rhs), $tval, $fval)>; diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td index 187145d3ac0..d91cdb8384e 100644 --- a/lib/Target/PowerPC/PPCInstrVSX.td +++ b/lib/Target/PowerPC/PPCInstrVSX.td @@ -958,27 +958,43 @@ def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>; // Selects. def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)), + (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)), (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)), + (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)), (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)), (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)), + (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)), (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)), + (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)), (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)), (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), + (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), + (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), + (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), + (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; +def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>; @@ -1060,18 +1076,27 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. (COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>; def : Pat<(f64 (fextend f32:$src)), (COPY_TO_REGCLASS $src, VSFRC)>; + def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), + (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; + def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), + (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; + def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), + (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; + def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), + (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; + def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), - (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>; + (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>; // VSX Elementary Scalar FP arithmetic (SP) let isCommutable = 1 in { diff --git a/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/test/CodeGen/PowerPC/select-i1-vs-i1.ll new file mode 100644 index 00000000000..6dabbaa4208 --- /dev/null +++ b/test/CodeGen/PowerPC/select-i1-vs-i1.ll @@ -0,0 +1,1685 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; FIXME: We should check the operands to the cr* logical operation itself, but +; unfortunately, FileCheck does not yet understand how to do arithmetic, so we +; can't do so without introducing a register-allocation dependency. + +define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32slt +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32ult +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32sle +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32ule +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32eq +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32sge +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32uge +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32sgt +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32ugt +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { +entry: + %cmp1 = icmp eq i32 %c3, %c4 + %cmp3tmp = icmp eq i32 %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i32 %a1, i32 %a2 + ret i32 %cond + +; CHECK-LABEL: @testi32ne +; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 +; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64slt +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64ult +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64sle +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64ule +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64eq +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64sge +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64uge +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64sgt +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64ugt +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { +entry: + %cmp1 = icmp eq i64 %c3, %c4 + %cmp3tmp = icmp eq i64 %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, i64 %a1, i64 %a2 + ret i64 %cond + +; CHECK-LABEL: @testi64ne +; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 +; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: isel 3, 7, 8, [[REG1]] +; CHECK: blr +} + +define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatslt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatsle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloateq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatsge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatuge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatsgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, float %a1, float %a2 + ret float %cond + +; CHECK-LABEL: @testfloatne +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoubleslt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoubleult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoublesle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoubleule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoubleeq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoublesge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoubleuge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoublesgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoubleugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { +entry: + %cmp1 = fcmp oeq double %c3, %c4 + %cmp3tmp = fcmp oeq double %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, double %a1, double %a2 + ret double %cond + +; CHECK-LABEL: @testdoublene +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: fmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; FIXME: This test (and the other v4f32 tests) should use the same bclr +; technique as the v2f64 tests below. + +; CHECK-LABEL: @testv4floatslt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatsle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floateq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatsge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatuge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatsgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testv4floatne +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 +; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: xxlor [[REG2]], 35, 35 +; CHECK: .LBB[[BB]]: +; CHECK: xxlor 34, [[REG2]], [[REG2]] +; CHECK: blr +} + +define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 { +entry: + %cmp1 = fcmp oeq ppc_fp128 %c3, %c4 + %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2 + ret ppc_fp128 %cond + +; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion +; works, we end up with two blocks with the same predicate. These could be +; combined. + +; CHECK-LABEL: @testppc_fp128eq +; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8 +; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7 +; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3 +; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]] +; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]] +; CHECK: fmr 9, 11 +; CHECK: .LBB[[BB1]]: +; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]] +; CHECK: fmr 10, 12 +; CHECK: .LBB[[BB2]]: +; CHECK-DAG: fmr 1, 9 +; CHECK-DAG: fmr 2, 10 +; CHECK: blr +} + +define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doubleslt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doubleult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doublesle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doubleule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doubleeq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doublesge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doubleuge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doublesgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doubleugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 + ret <2 x double> %cond + +; CHECK-LABEL: @testv2doublene +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: vor 2, 3, 3 +; CHECK: blr +} + +define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doubleslt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doubleult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doublesle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doubleule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doubleeq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doublesge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doubleuge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doublesgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doubleugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 + ret <4 x double> %cond + +; CHECK-LABEL: @testqv4doublene +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatslt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatsle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floateq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatsge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatuge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatsgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 + ret <4 x float> %cond + +; CHECK-LABEL: @testqv4floatne +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1slt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1ult +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1sle +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1ule +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1eq +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1sge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1uge +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1sgt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1ugt +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { +entry: + %cmp1 = fcmp oeq float %c3, %c4 + %cmp3tmp = fcmp oeq float %c1, %c2 + %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 + %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 + ret <4 x i1> %cond + +; CHECK-LABEL: @testqv4i1ne +; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: qvfmr 5, 6 +; CHECK: .LBB[[BB]]: +; CHECK: qvfmr 1, 5 +; CHECK: blr +} + +attributes #0 = { nounwind readnone "target-cpu"="pwr7" } +attributes #1 = { nounwind readnone "target-cpu"="a2q" } + -- 2.34.1