From fdd9f006bceaa4f24a969d1411917b9558cd156d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 14 Sep 2007 01:57:02 +0000 Subject: [PATCH] Fix comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index cd504139ae5..2f1990e0170 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -157,8 +157,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(PPC::R0, false, false, true), FrameIdx); } else if (RC == PPC::VRRCRegisterClass) { // We don't have indexed addressing for vector loads. Emit: - // R11 = ADDI FI# - // Dest = LVX R0, R11 + // R0 = ADDI FI# + // STVX VAL, 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), @@ -210,8 +210,8 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); } else if (RC == PPC::VRRCRegisterClass) { // We don't have indexed addressing for vector loads. Emit: - // R11 = ADDI FI# - // Dest = LVX R0, R11 + // R0 = ADDI FI# + // Dest = LVX 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), -- 2.34.1