From fe1c8d94f2fc9a1bfcb4b58dbe9f86c7ae076300 Mon Sep 17 00:00:00 2001
From: chenxing <chenxing@rock-chips.com>
Date: Wed, 10 Jul 2013 11:04:55 +0800
Subject: [PATCH] rk3188: set new leakage level and delayline bounds to fit
 avdd_com shoted with vdd_arm

---
 arch/arm/mach-rk3188/dvfs.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rk3188/dvfs.c b/arch/arm/mach-rk3188/dvfs.c
index 6b372c1d9ecf..b3f69742e207 100755
--- a/arch/arm/mach-rk3188/dvfs.c
+++ b/arch/arm/mach-rk3188/dvfs.c
@@ -82,18 +82,26 @@ struct lkg_maxvolt {
 	int leakage_level;
 	unsigned int maxvolt;
 };
+#if 0
+/* avdd_com & vdd_arm separate circuit */
 static struct lkg_maxvolt lkg_volt_table[] = {
 	{.leakage_level = 1,	.maxvolt = 1350 * 1000},
 	{.leakage_level = 3,	.maxvolt = 1275 * 1000},
 	{.leakage_level = 15,	.maxvolt = 1200 * 1000},
 };
-
+#else
+/* avdd_com & vdd_arm short circuit */
+static struct lkg_maxvolt lkg_volt_table[] = {
+	{.leakage_level = 3,	.maxvolt = 1350 * 1000},
+	{.leakage_level = 15,	.maxvolt = 1250 * 1000},
+};
+#endif
 static int leakage_level = 0;
 #define MHZ	(1000 * 1000)
 #define KHZ	(1000)
 // Delayline bound for nandc = 148.5MHz, Varm = Vlog = 1.00V
 #define HIGH_DELAYLINE	125
-#define LOW_DELAYLINE	110
+#define LOW_DELAYLINE	125
 static u8 rk30_get_avs_val(void);
 void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table)
 {
-- 
2.34.1