From fe8dc2e2c8d921c5b32ab3e338b24c07e4b9f14e Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 7 Aug 2006 22:16:08 +0000 Subject: [PATCH] Move DAGSize to SelectionDAGISel; it's used in tablegen'd isel code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29547 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGISel.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index e5d024a892f..f439f21d6fa 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -17,10 +17,10 @@ #include "llvm/Pass.h" #include "llvm/Constant.h" +#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" namespace llvm { - class SelectionDAG; class SelectionDAGLowering; class SDOperand; class SSARegMap; @@ -39,8 +39,10 @@ public: SSARegMap *RegMap; SelectionDAG *CurDAG; MachineBasicBlock *BB; + std::vector TopOrder; + unsigned DAGSize; - SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {} + SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0), JT(0,0,0,0) {} TargetLowering &getTargetLowering() { return TLI; } @@ -52,6 +54,9 @@ public: virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {} virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0; + virtual void SelectRootInit() { + DAGSize = CurDAG->AssignTopologicalOrder(TopOrder); + } /// SelectInlineAsmMemoryOperand - Select the specified address as a target /// addressing mode, according to the specified constraint code. If this does -- 2.34.1