From ffba4501906f5c696d463912dc6edce01e68ef22 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Fri, 26 Dec 2014 19:31:46 +0000 Subject: [PATCH] [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224868 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 6 +-- lib/Target/Hexagon/HexagonInstrInfo.cpp | 24 +++++----- lib/Target/Hexagon/HexagonInstrInfo.td | 56 ++++------------------ test/MC/Disassembler/Hexagon/ld.txt | 36 ++++++++++++++ 4 files changed, 61 insertions(+), 61 deletions(-) diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index ab8e20ef21c..487df1b4899 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -595,17 +595,17 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) { TM.getSubtargetImpl()->getInstrInfo()); if (LoadedVT == MVT::i64) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = Hexagon::POST_LDrid; + Opcode = Hexagon::L2_loadrd_pi; else Opcode = Hexagon::L2_loadrd_io; } else if (LoadedVT == MVT::i32) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = Hexagon::POST_LDriw; + Opcode = Hexagon::L2_loadri_pi; else Opcode = Hexagon::L2_loadri_io; } else if (LoadedVT == MVT::i16) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih; + Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi; else Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io; } else if (LoadedVT == MVT::i8) { diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index f74c0231104..bbff6f6c45d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -684,14 +684,14 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::L2_loadrub_io: return isUInt<6>(MI->getOperand(2).getImm()); - case Hexagon::POST_LDrid: + case Hexagon::L2_loadrd_pi: return isShiftedInt<4,3>(MI->getOperand(3).getImm()); - case Hexagon::POST_LDriw: + case Hexagon::L2_loadri_pi: return isShiftedInt<4,2>(MI->getOperand(3).getImm()); - case Hexagon::POST_LDrih: - case Hexagon::POST_LDriuh: + case Hexagon::L2_loadrh_pi: + case Hexagon::L2_loadruh_pi: return isShiftedInt<4,1>(MI->getOperand(3).getImm()); case Hexagon::L2_loadrb_pi: @@ -1357,16 +1357,16 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::L2_ploadrubt_io: case Hexagon::L2_ploadrubf_io: return true; - case Hexagon::POST_LDrid_cPt : - case Hexagon::POST_LDrid_cNotPt : - case Hexagon::POST_LDriw_cPt : - case Hexagon::POST_LDriw_cNotPt : - case Hexagon::POST_LDrih_cPt : - case Hexagon::POST_LDrih_cNotPt : + case Hexagon::L2_ploadrdt_pi : + case Hexagon::L2_ploadrdf_pi : + case Hexagon::L2_ploadrit_pi : + case Hexagon::L2_ploadrif_pi : + case Hexagon::L2_ploadrht_pi : + case Hexagon::L2_ploadrhf_pi : case Hexagon::L2_ploadrbt_pi : case Hexagon::L2_ploadrbf_pi : - case Hexagon::POST_LDriuh_cPt : - case Hexagon::POST_LDriuh_cNotPt : + case Hexagon::L2_ploadruht_pi : + case Hexagon::L2_ploadruhf_pi : case Hexagon::L2_ploadrubt_pi : case Hexagon::L2_ploadrubf_pi : return QRI.Subtarget.hasV4TOps(); diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 172a5aff1ca..b8a81a8023b 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1701,55 +1701,19 @@ let accessSize = ByteAccess, isCodeGenOnly = 0 in { defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>; } -multiclass LD_PostInc_Pbase { - let isPredicatedNew = isPredNew in - def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"($src2++#$offset)", - [], - "$src2 = $dst2">; -} - -multiclass LD_PostInc_Pred { - let isPredicatedFalse = PredNot in { - defm _c#NAME : LD_PostInc_Pbase; - // Predicate new - let Predicates = [HasV4T], validSubTargets = HasV4SubT in - defm _cdn#NAME#_V4 : LD_PostInc_Pbase; - } +// post increment halfword loads with immediate offset +let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in { + defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>; + defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>; } -multiclass LD_PostInc2 { - - let BaseOpcode = "POST_"#BaseOp in { - let isPredicable = 1 in - def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2), - (ins IntRegs:$src1, ImmOp:$offset), - "$dst = "#mnemonic#"($src1++#$offset)", - [], - "$src1 = $dst2">; - - let isPredicated = 1 in { - defm Pt : LD_PostInc_Pred; - defm NotPt : LD_PostInc_Pred; - } - } -} +// post increment word loads with immediate offset +let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in +defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>; -let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in { - defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>, - PredNewRel; - defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>, - PredNewRel; - defm POST_LDriw : LD_PostInc2<"memw", "LDriw", IntRegs, s4_2Imm>, - PredNewRel; - defm POST_LDrid : LD_PostInc2<"memd", "LDrid", DoubleRegs, s4_3Imm>, - PredNewRel; -} +// post increment doubleword loads with immediate offset +let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in +defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>; def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)), (i32 (L2_loadrb_io AddrFI:$addr, 0)) >; diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt index 2c967fbe5c5..a222e5b055b 100644 --- a/test/MC/Disassembler/Hexagon/ld.txt +++ b/test/MC/Disassembler/Hexagon/ld.txt @@ -2,6 +2,8 @@ 0x70 0xd8 0xd5 0x41 # CHECK: if (p3) r17:16 = memd(r21 + #24) +0xb0 0xc0 0xd5 0x9b +# CHECK: r17:16 = memd(r21++#40) 0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43 # CHECK: p3 = r5 # CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24) @@ -10,6 +12,16 @@ 0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24) +0xb0 0xe6 0xd5 0x9b +# CHECK: if (p3) r17:16 = memd(r21++#40) +0xb0 0xee 0xd5 0x9b +# CHECK: if (!p3) r17:16 = memd(r21++#40) +0x03 0x40 0x45 0x85 0xb0 0xf6 0xd5 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17:16 = memd(r21++#40) +0x03 0x40 0x45 0x85 0xb0 0xfe 0xd5 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40) 0xf1 0xc3 0x15 0x91 # CHECK: r17 = memb(r21 + #31) @@ -38,6 +50,18 @@ 0xf1 0xc3 0x55 0x91 # CHECK: r17 = memh(r21 + #62) +0xb1 0xc0 0x55 0x9b +# CHECK: r17 = memh(r21++#10) +0xb1 0xe6 0x55 0x9b +# CHECK: if (p3) r17 = memh(r21++#10) +0xb1 0xee 0x55 0x9b +# CHECK: if (!p3) r17 = memh(r21++#10) +0x03 0x40 0x45 0x85 0xb1 0xf6 0x55 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memh(r21++#10) +0x03 0x40 0x45 0x85 0xb1 0xfe 0x55 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10) 0xf1 0xc3 0x35 0x91 # CHECK: r17 = memub(r21 + #31) @@ -66,6 +90,8 @@ 0xb1 0xc2 0x75 0x91 # CHECK: r17 = memuh(r21 + #42) +0xb1 0xc0 0x75 0x9b +# CHECK: r17 = memuh(r21++#10) 0xb1 0xda 0x75 0x41 # CHECK: if (p3) r17 = memuh(r21 + #42) 0xb1 0xda 0x75 0x45 @@ -76,6 +102,16 @@ 0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42) +0xb1 0xe6 0x75 0x9b +# CHECK: if (p3) r17 = memuh(r21++#10) +0xb1 0xee 0x75 0x9b +# CHECK: if (!p3) r17 = memuh(r21++#10) +0x03 0x40 0x45 0x85 0xb1 0xf6 0x75 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memuh(r21++#10) +0x03 0x40 0x45 0x85 0xb1 0xfe 0x75 0x9b +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10) 0xb1 0xc2 0x95 0x91 # CHECK: r17 = memw(r21 + #84) -- 2.34.1