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R600/SI: Avoid generating S_MOVs with 64-bit immediates v2
2013-04-05 Tom StellardR600/SI: Avoid generating S_MOVs with 64-bit immediates v2
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2013-03-08 Tom StellardR600: Optimize another selectcc case
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2013-03-08 Tom StellardR600: Improve custom lowering of select_cc
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2013-03-08 Tom StellardR600: Change operation action from Custom to Expand...
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2013-03-08 Tom StellardR600: Change operation action from Custom to Expand...
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2013-03-08 Tom StellardR600: Set BooleanContents to ZeroOrNegativeOneBooleanContent
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2013-03-08 Tom StellardLegalizeDAG: Respect the result of TLI.getBooleanContents...
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2013-03-08 Tom StellardDAGCombiner: Use correct value type for checking legality...
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2013-03-04 Tom StellardR600: Clean up datalayout strings so they better match...
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2013-02-21 Tom StellardR600: Fix for Unigine when MachineSched is enabled
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-19 Tom StellardR600: Add AR_X to the R600_TReg_X register class.
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2013-02-19 Tom StellardR600: Mark all members of the TRegMem register class...
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2013-02-19 Tom StellardR600: Fix scheduler crash caused by invalid MachinePointerInfo
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2013-02-19 Tom StellardR600: Fix tracking of implicit defs in the IndirectAddressin...
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2013-02-13 Tom StellardR600: Add support for 128-bit parameters
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2013-02-08 Tom StellardReleaseNotes: Add section for R600 backend
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2013-02-08 Tom StellardR600: Dump the function name when TargetLowering::LowerCall...
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2013-02-08 Tom StellardR600: rework flow creation in the structurizer v2
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2013-02-08 Tom StellardR600: fix loop analyses in the structurizer
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2013-02-08 Tom StellardR600: fix PHI value adding in the structurizer
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2013-02-07 Tom StellardR600/SI: cleanup VGPR encoding
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600/SI: Handle VGPR64 destination in copyPhysReg().
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600/SI: Add pattern for mul.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600/SI: simplify and fix SMRD encoding
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600/SI: add proper 64bit immediate support v2
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600: Add an explicit default processor
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2013-02-07 Tom StellardR600/SI: Use proper instructions for array/shadow samplers.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600/SI: Make sample intrinsic address parameter type...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600/SI: Add basic support for more integer vector...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600: Consolidate sub register indices.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-07 Tom StellardR600: Add support for SET*_DX10 instructions
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2013-02-07 Tom StellardR600: Add tests for unsupported condition codes.
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2013-02-07 Tom StellardR600: Fix assembly name for SETGT_INT
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2013-02-06 Tom StellardR600: Support for indirect addressing v4
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2013-02-05 Tom StellardR600: Fold remaining CONST_COPY after expand pseudo...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-05 Tom StellardR600: improve inputs/interpolation handling
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-02-05 Tom StellardR600: Add tests for instruction predicates
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2013-02-05 Tom StellardR600: Emit function name in the AsmPrinter
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2013-02-05 Tom StellardR600/SI: Add patterns for fcos and fsin.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-31 Tom StellardR600: Fold clamp, neg, abs
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-31 Tom StellardR600: Consider bitcast when folding const_address node.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-31 Tom StellardR600: Make store_dummy intrinsic more general by passing...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-23 Tom StellardR600: Add a llvm.R600.store.swizzle intrinsics
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-23 Tom StellardR600: Simplify stream outputs intrinsic
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-23 Tom StellardR600: rework handling of the constants
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-23 Tom StellardR600: Add a CONST_ADDRESS node to model constant buf...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-23 Tom StellardR600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen def
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-21 Tom StellardR600/SI: Use unnormalized coordinates for sampling...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-21 Tom StellardR600/SI: Take target parameter for sample intrinsics.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-21 Tom StellardR600/SI: Derive all sample intrinsics from a single...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-18 Tom StellardR600: Proper insert S_WAITCNT instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-18 Tom StellardR600: Optimize and cleanup KILL on SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-01-02 Tom StellardDAGCombiner: Avoid generating illegal vector INT_TO_FP...
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2012-12-21 Tom StellardR600: Coding style - remove empty spaces from the beginning...
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2012-12-21 Tom StellardR600: Fix MAX_UINT definition
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2012-12-21 Tom StellardR600: Add SHADOWCUBE to TEX_SHADOW pattern
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2012-12-21 Tom StellardR600: Expand vec4 INT <-> FP conversions
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2012-12-19 Tom StellardR600: Add entry in CODE_OWNERS.TXT
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2012-12-19 Tom StellardR600: Remove unecessary VREG alignment.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2012-12-19 Tom StellardR600: control flow optimization
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2012-12-19 Tom StellardR600: New control flow for SI v2
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2012-12-17 Tom StellardR600: enable S_*N2_* instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2012-12-17 Tom StellardR600: BB operand support for SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2012-12-17 Tom StellardR600: remove nonsense setPrefLoopAlignment
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2012-12-13 Tom StellardFix warnings with -DNDEBUG
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2012-12-11 Tom StellardAdd R600 backend
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2012-12-10 Tom StellardLegalizeDAG: Allow type promotion of scalar loads
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2012-12-10 Tom StellardLegalizeDAG: Allow type promotion for scalar stores
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2012-09-18 Tom StellardMake MachinePostDominatorTree::DT private
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2012-09-17 Tom StellardAdd a MachinePostDominator pass
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2012-09-06 Tom StellardTablegen: Add OperandWithDefaultOps Operand type
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2012-07-16 Tom StellardRevert "AMDGPU: Add core backend files for R600/SI...
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2012-07-16 Tom StellardRevert "include/llvm: Add R600 Intrinsics v6"
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2012-07-16 Tom StellardRevert "Build script changes for R600/SI Codegen v6"
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2012-07-16 Tom StellardRevert "test/CodeGen/R600: Add some basic tests v6"
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2012-07-16 Tom StellardRevert "Target/AMDGPU/R600KernelParameters.cpp: Fix...
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2012-07-16 Tom StellardRevert "Target/AMDGPU: [CMake] Fix dependencies. 1...
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2012-07-16 Tom StellardRevert "Target/AMDGPU/R600KernelParameters.cpp: Don...
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2012-07-16 Tom StellardRevert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unrea...
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2012-07-16 Tom StellardRevert "Target/AMDGPU: Fix includes, or msvc build...
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2012-07-16 Tom Stellardtest/CodeGen/R600: Add some basic tests v6
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2012-07-16 Tom StellardBuild script changes for R600/SI Codegen v6
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2012-07-16 Tom Stellardinclude/llvm: Add R600 Intrinsics v6
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2012-07-16 Tom StellardAMDGPU: Add core backend files for R600/SI codegen v6
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2012-07-11 Tom Stellardtest commit
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C/C++ LLVM-based compilers that forbids OOTA behaviors