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Improve PPC VR (Altivec) register spilling
2013-03-14 Vincent LejeuneR600: Factorize code handling Const Read Port limitation
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2013-03-13 Vincent LejeuneR600: Remove unused Outputs variable
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2013-03-11 Vincent LejeuneR600: Fix JUMP handling so that MachineInstr verification...
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2013-03-08 Vincent LejeuneR600: Change addresspace in fold-kcache.ll
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2013-03-05 Vincent LejeuneR600: Do not predicate vector op
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2013-03-05 Vincent LejeuneR600: initial scheduler code
Vincent Lejeune:
Vincent Lejeune: [v2]
Vincent Lejeune: [v3]
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2013-03-05 Vincent LejeuneR600: Remove LowerConstCopyPass and lower CONST_COPY...
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2013-03-05 Vincent LejeuneR600: Turn BUILD_VECTOR into Reg_Sequence
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2013-03-05 Vincent LejeuneR600: CONST_ADDRESS node is not marked as mayLoad anymore
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2013-03-05 Vincent LejeuneR600: Use MUL_IEEE for trig/fdiv intrinsic
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2013-03-05 Vincent LejeuneR600: Add support for indirect addressing of non default...
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2013-02-18 Vincent LejeuneR600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for...
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2013-02-18 Vincent LejeuneR600: Support for TBO
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2013-02-18 Vincent LejeuneR600: Increase number of ArrayBase Reg to 32
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2013-02-14 Vincent LejeuneR600: Do not fold single instruction with more that...
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2013-02-14 Vincent LejeuneR600: Export instructions are no longer terminator
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2013-02-14 Vincent LejeuneR600: Fold zero/one in export instructions
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2013-02-14 Vincent LejeuneR600: Do not fold modifier/litterals in vector inst
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2013-02-10 Vincent LejeuneTest Commit - Remove some trailing whitespace in R600Instruc...
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C/C++ LLVM-based compilers that forbids OOTA behaviors