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SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 Tom StellardSimplifyCFG: Use parallel-and and parallel-or mode...
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2013-07-23 Tom StellardDAGCombiner: Pass the correct type to TargetLowering...
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2013-07-23 Tom StellardR600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS...
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2013-07-23 Tom StellardR600: Add support for 24-bit MAD instructions
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2013-07-23 Tom StellardR600: Add support for 24-bit MUL instructions
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2013-07-23 Tom StellardR600: Improve support for < 32-bit loads
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2013-07-23 Tom StellardR600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cpp
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2013-07-23 Tom StellardR600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel...
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2013-07-23 Tom StellardR600: Use KCache for kernel arguments
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2013-07-23 Tom StellardR600: Simplify assembly for KCache registers using...
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2013-07-23 Tom StellardR600: Use the same compute kernel calling convention...
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2013-07-23 Tom StellardR600: Use correct LoadExtType when lowering kernel...
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2013-07-23 Tom StellardR600: Clean up extended load patterns
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2013-07-23 Tom StellardR600: Expand vector FNEG
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2013-07-18 Tom StellardR600/SI: Fix crash with VSELECT
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2013-07-18 Tom StellardR600/SI: Add support for v2f32 loads
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2013-07-18 Tom StellardR600/SI: Add support for v2f32 stores
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2013-07-18 Tom StellardR600: Expand VSELECT for all types
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2013-07-15 Tom StellardR600/SI: Add support for 64-bit loads
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2013-07-12 Tom StellardR600: Remove the fpconst64.ll test which was failing...
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2013-07-12 Tom StellardR600/SI: Add support for f64 kernel arguments
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-07-12 Tom StellardR600/SI: Implement select and compares for SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-07-12 Tom StellardR600/SI: Add fsqrt pattern for SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-07-12 Tom StellardR600/SI: Add double precision fsub pattern for SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-07-12 Tom StellardR600/SI: SI support for 64bit ConstantFP
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-07-12 Tom StellardR600/SI: Add initial double precision support for SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-07-12 Tom StellardR600: Add ISA documents to the CompilerWriterInfo page
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2013-06-28 Tom StellardR600/SI: Add processor types for each CIK variant
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-06-28 Tom StellardR600: Add local memory support via LDS
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2013-06-28 Tom StellardR600: Add support for GROUP_BARRIER instruction
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2013-06-28 Tom StellardR600: Add ALUInst bit to tablegen definitions v2
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2013-06-27 Tom StellardR600: Remove alu-split.ll test
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2013-06-25 Tom StellardR600: Use new getNamedOperandIdx function generated...
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2013-06-25 Tom StellardTableGen: Generate a function for getting operand indices...
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2013-06-25 Tom StellardR600/SI: Report unaligned memory accesses as legal...
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2013-06-25 Tom StellardR600: Add support for i32 loads from the constant address...
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2013-06-25 Tom StellardR600/SI: Add support for v4i32 and v4f32 kernel args
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2013-06-25 Tom StellardR600: Fix typo in R600Schedule.td
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2013-06-20 Tom StellardR600/SI: Expand sub for v2i32 and v4i32 for SI
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-06-20 Tom StellardR600/SI: Expand add for v2i32 and v4i32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-06-20 Tom StellardR600: Expand v2i32 load/store instead of custom lowering
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-06-15 Tom StellardR600: Add SI load support for v[24]i32 and store for...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-06-14 Tom StellardR600: Use correct encoding for Vertex Fetch instructions...
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2013-06-14 Tom StellardR600: Use EXPORT_RAT_INST_STORE_DWORD for stores on...
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2013-06-14 Tom StellardR600: Factor the instruction encoding out the RAT_WRITE_CACH...
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2013-06-14 Tom StellardR600: Move instruction encoding definitions into a...
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2013-06-13 Tom StellardR600: Don't try to fix reg class when copying IMPLICIT_DEF...
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2013-06-07 Tom StellardR600: Fix calculation of stack offset in AMDGPUFrameLowering
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2013-06-07 Tom StellardR600: Rework subtarget info and remove AMDILDevice...
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2013-06-07 Tom StellardR600: Fix the fetch limits for R600 generation GPUs
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2013-06-07 Tom StellardR600: Move Subtarget feature definitions into AMDGPU.td
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2013-06-07 Tom StellardR600: Remove unnecessary include
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2013-06-05 Tom StellardR600: Replace predicate loop with predicate function
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2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
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2013-06-03 Tom StellardR600/SI: Add support for work item and work group intrinsics
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2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
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2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
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2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class...
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2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass()
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2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITargetLo...
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2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessISelDAG()
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2013-06-03 Tom StellardR600/SI: Add support for global loads
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2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions
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2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
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2013-05-20 Tom StellardR600: Fix rotr.ll on non-asserts builds
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2013-05-20 Tom StellardR600/SI: Use a multiclass for MUBUF_Load_Helper
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2013-05-20 Tom StellardR600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
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2013-05-20 Tom StellardR600/SI: Add pattern for rotr
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2013-05-20 Tom StellardR600: Swap the legality of rotl and rotr
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2013-05-20 Tom StellardR600/SI: Add patterns for 64-bit shift operations
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2013-05-20 Tom StellardR600/SI: Use the same names for VOP3 operands and encoding...
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2013-05-20 Tom StellardR600/SI: Make fitsRegClass() operands const
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2013-05-17 Tom StellardR600: Fix encoding for R600 family GPUs
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2013-05-17 Tom StellardR600: Pass MCSubtargetInfo reference to R600CodeEmitter
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2013-05-14 Tom StellardR600/SI: Add processor type for Hainan asic
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-10 Tom StellardR600: Remove AMDILPeeopholeOptimizer and replace optimizatio...
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2013-05-10 Tom StellardR600: Expand SUB for v2i32/v4i32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-10 Tom StellardR600: Expand MUL for v4i32/v2i32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-10 Tom StellardR600: Expand SRA for v4i32/v2i32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-10 Tom StellardR600: Expand vselect for v4i32 and v2i32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600/SI: Handle arbitrary destination type in SITargetLoweri...
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600/SI: Add intrinsic for texture image loading
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600/SI: Add pattern for uint_to_fp
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600/SI: Add patterns for integer maxima / minima
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600/SI: Add pattern for AMDGPU.trunc intrinsic
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-05-06 Tom StellardR600: Remove dead code from the CodeEmitter v2
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2013-05-06 Tom StellardR600: Emit config values in register / value pairs
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2013-05-06 Tom StellardR600: Stop emitting the instruction type byte before...
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2013-05-06 Tom StellardR600: Emit ISA for CALL_FS_* instructions
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2013-05-03 Tom StellardR600: Expand vector or, shl, srl, and xor nodes
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2013-05-03 Tom StellardR600: BFI_INT is a vector-only instruction
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2013-05-03 Tom StellardR600: Add pattern for SHA-256 Ma function
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2013-05-03 Tom StellardR600: Clean up comments in Processors.td
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2013-05-02 Tom StellardR600: Use new tablegen syntax for patterns
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2013-05-02 Tom StellardR600/SI: remove nonsense select pattern
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2013-04-29 Tom StellardR600: Use correct CF_END instruction on Northern Island...
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2013-04-29 Tom StellardR600: Fix encoding of CF_END_{EG, R600} instructions
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2013-04-26 Tom StellardR600: Initialize AMDGPUMachineFunction::ShaderType...
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2013-04-24 Tom StellardR600: Initialize BooleanVectorContents
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C/C++ LLVM-based compilers that forbids OOTA behaviors