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[ARM64] Properly support both apple and standard syntax for FMOV
2014-04-07 Tom StellardR600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
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2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
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2014-04-07 Tom StellardR600: Replace dyn_cast + assert with cast
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2014-04-03 Tom StellardR600: Correct opcode for BFE_INT
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2014-04-03 Tom StellardR600/SI: Lower 64-bit immediates using REG_SEQUENCE
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2014-04-02 Tom StellardTargetLibraryInfo: Disable memcpy and memset on R600
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2014-03-31 Tom StellardR600/SI: Implement SIInstrInfo::isTriviallyRematerializable()
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2014-03-31 Tom StellardR600/SI: Lower i64 SELECT by bitcasting to a vector...
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2014-03-31 Tom StellardR600/SI: Return the correct index for VGPRs in getHWRegIndex()
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2014-03-24 Tom StellardR600/SI: Fix warning with gcc 4.8.2
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2014-03-24 Tom StellardR600/SI: Promote fp64 SELECT to i64
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2014-03-24 Tom StellardSelectionDAG: Allow promotion of SELECT nodes from...
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2014-03-24 Tom StellardR600: Reorganize tablegen instruction definitions
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2014-03-21 Tom StellardR600/SI: Handle MUBUF instructions in SIInstrInfo:...
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2014-03-21 Tom StellardR600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
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2014-03-21 Tom StellardR600/SI: Use SGPR_(32|64) reg clases when lowering...
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2014-03-21 Tom StellardSink: Don't sink static allocas from the entry block
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2014-03-17 Tom StellardR600/SI: Fix implementation of isInlineConstant() used...
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2014-03-17 Tom StellardR600/SI: Use correct dest register class for V_READFIRSTLANE_B32
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2014-03-17 Tom StellardR600/SI: Add generic checks to SIInstrInfo::verifyInstruction()
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2014-03-13 Tom StellardR600: LDS instructions shouldn't implicitly define...
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2014-03-07 Tom StellardR600/SI: Using SGPRs is illegal for instructions that...
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2014-03-07 Tom StellardR600/SI: Custom lower i1 stores
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2014-03-03 Tom StellardAdd patch level to llvm version in CMake and Autoconf
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2014-02-28 Tom StellardR600: Verify all instructions in the AsmPrinter on...
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2014-02-28 Tom StellardR600/SI: Expand all v16[if]32 operations
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2014-02-25 Tom StellardR600: Don't unconditionally unroll loops with private...
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2014-02-25 Tom StellardR600/SI: Custom select 64-bit ADD
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2014-02-14 Tom StellardTargetLowering: n * r where n > 2 should be an illegal...
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2014-02-13 Tom StellardR600/SI: Expand all v8[if]32 operations
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2014-02-13 Tom StellardR600/SI: Add a pattern for i32 anyext
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2014-02-13 Tom StellardR600/SI: Completely Disable TypeRewriter on compute
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2014-02-13 Tom StellardR600/SI: Split global vector loads with more than 4...
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2014-02-13 Tom StellardR600/SI: Add ShaderType attribute to some tests
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2014-02-10 Tom StellardR600/SI: Initialize M0 and emit S_WQM_B64 whenever...
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2014-02-10 Tom StellardR600/SI: Only use S_WQM_B64 in pixel shaders
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2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Reg+Imm offsets
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2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Imm offsets
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2014-02-06 Tom StellardR600/SI: Add a MUBUF load pattern for Reg+Imm offsets
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2014-02-06 Tom StellardR600/SI: Use immediates offsets for SMRD instructions...
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2014-02-04 Tom StellardR600/SI: Expand i1 BR_CC
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2014-02-04 Tom StellardR600/SI: Don't assume copies will be coalesced in SIFixSGPRC...
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2014-02-04 Tom StellardR600/SI: Custom lower i64 ISD::SELECT
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2014-02-04 Tom StellardR600: Enable vector fpow.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-02-04 Tom StellardHowToReleaseLLVM: Add information about dot releases
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2014-01-23 Tom StellardR600: Remove successive JUMP in AnalyzeBranch when...
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2014-01-23 Tom StellardR600: Disable the BFE pattern
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2014-01-23 Tom StellardR600: Correctly handle vertex fetch clauses the precede...
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2014-01-23 Tom StellardR600: Unconditionally unroll loops that contain GEPs...
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2014-01-23 Tom StellardR600: Recommit 199842: Add work-around for the CF stack...
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2014-01-22 Tom StellardRevert "R600: Add work-around for the CF stack entry...
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2014-01-22 Tom StellardR600: Add work-around for the CF stack entry HW bug
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2014-01-22 Tom StellardR600: Add some missing CF instruction definitions to...
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2014-01-22 Tom StellardR600: Refactor stack size calculation
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2014-01-22 Tom StellardR600: CF_PUSH is the same on Evergreen and Cayman
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2014-01-22 Tom StellardR600: Add wavefront size property to the subtargets v2
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2014-01-22 Tom StellardR600: Add stack size to .AMDGPUcsdata section
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2014-01-22 Tom StellardR600: MOVA is vector only
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2014-01-22 Tom StellardR600: Take alignment into account when calculating...
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2014-01-22 Tom StellardR600: Add support for global addresses with constant...
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2014-01-22 Tom StellardR600: Begin private memory at the second GPR.
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2014-01-22 Tom StellardR600/SI: Add support for i8 and i16 private loads/stores
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2013-12-20 Tom StellardR600: Allow ftrunc
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-12-11 Tom StellardR600: Re-format Processors.td
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2013-12-11 Tom StellardR600: Register AMDGPUCFGStructurizer pass
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2013-12-11 Tom StellardR600: Register R600EmitClauseMarkers pass
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2013-11-27 Tom StellardR600: Expand vector FABS
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2013-11-27 Tom StellardR600/SI: Implement spilling of SGPRs v5
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2013-11-27 Tom StellardR600/SI: Use SGPR_32 register class for 32-bit SMRD...
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2013-11-27 Tom StellardR600: Add support for ISD::FROUND
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2013-11-22 Tom StellardR600/SI: Fixing handling of condition codes
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2013-11-22 Tom StellardR600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
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2013-11-22 Tom StellardSelectionDAG: Optimize expansion of vec_type = BITCAST...
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2013-11-22 Tom StellardSplit SETCC if VSELECT requires splitting too.
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2013-11-18 Tom StellardR600: Enable the IR structurizer by default
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2013-11-18 Tom StellardR600: Fix a crash in the AMDILCFGStrucurizer
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2013-11-18 Tom StellardR600: Add a SubtargetFeatture for disabling the ifcvt...
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2013-11-18 Tom StellardR600: Use lower-case for EnableIRStructurizer feature
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2013-11-18 Tom StellardR600/SI: Fix illegal VGPR->SGPR copy inside of loop
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2013-11-18 Tom StellardR600/SI: Fix another case of illegal VGPR->SGPR copy
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2013-11-15 Tom StellardR600/SI: Add VReg_96 register class to SIRegisterInfo...
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2013-11-15 Tom StellardR600: Fix scheduling of instructions that use the LDS...
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2013-11-14 Tom StellardR600/SI: Add processor type for Hawaii
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-11-13 Tom StellardR600: Fix uninitialized variable usage
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2013-11-13 Tom StellardR600/SI: Add support for private address space load...
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2013-11-13 Tom StellardR600/SI: Prefer SALU instructions for bit shift operations
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2013-10-30 Tom StellardR600: Custom lower f32 = uint_to_fp i64
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2013-10-29 Tom StellardR600/SI: Add compute support for CI v2
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2013-10-29 Tom StellardR600: Expand vector FSQRT ops
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2013-10-24 Tom StellardInliner: Handle readonly attribute per argument when...
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2013-10-23 Tom StellardR600/SI: Replace ffs(x) - 1 with countTrailingZeros(x)
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2013-10-23 Tom StellardR600/SI: fix MIMG writemask adjustement
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2013-10-23 Tom StellardR600: Fix handling of vector kernel arguments
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2013-10-23 Tom StellardSelectionDAG: Pass along the original argument/element...
Tom Stellard:
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2013-10-23 Tom StellardR600/SI: Add support for i64 bitwise or
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2013-10-23 Tom StellardR600/SI: Use S_LOAD_DWORD instructions for v8i32 and...
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2013-10-22 Tom StellardR600/SI: Use llvm_unreachable() for an always false...
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2013-10-22 Tom StellardR600/SI: Fix warning on non-asserts build
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2013-10-22 Tom StellardR600: Simplify handling of private address space
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2013-10-22 Tom StellardR600: Remove unused InstrInfo::getMovImmInstr() function
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C/C++ LLVM-based compilers that forbids OOTA behaviors