projects / oota-llvm.git / search
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
CodeGen: add parenthesis around complex expression
2014-05-10 Vincent LejeuneR600/SI: Fold fabs/fneg into src input modifier
 commit | commitdiff | tree
2014-05-10 Vincent LejeuneR600/SI: Prettier display of input modifiers
 commit | commitdiff | tree
2014-05-10 Vincent LejeuneR600/SI: Use pseudo instruction for fabs/clamp/fneg
 commit | commitdiff | tree
2013-12-10 Vincent LejeuneR600: Fix an infinite loop when trying to reorganize...
commit | commitdiff | tree
2013-12-10 Vincent LejeuneR600: Fix input modifiers lost for Cayman
 commit | commitdiff | tree
2013-12-07 Vincent LejeuneAdd a RequireStructuredCFG Field to TargetMachine.
 commit | commitdiff | tree
2013-12-07 Vincent LejeuneR600: Remove orphaned declarations
 commit | commitdiff | tree
2013-12-02 Vincent LejeuneR600: Workaround for cayman loop bug
 commit | commitdiff | tree
2013-11-16 Vincent LejeuneR600: Make dot_4 instructions predicable
 commit | commitdiff | tree
2013-11-12 Vincent LejeuneR600: Reenable llvm.R600.load.input/interp.input for...
commit | commitdiff | tree
2013-11-11 Vincent LejeuneR600: Use function inputs to represent data stored...
commit | commitdiff | tree
2013-11-06 Vincent LejeuneR600: Fix LowerUDIVREM
 commit | commitdiff | tree
2013-10-15 Vincent LejeuneR600/SI: Remove some leftover MI dump call
 commit | commitdiff | tree
2013-10-13 Vincent LejeuneR600: improve dump of S_WAITCNT
 commit | commitdiff | tree
2013-10-13 Vincent LejeuneR600/SI: Add SinkingPass before ISel
 commit | commitdiff | tree
2013-10-13 Vincent LejeuneR600/SI: Support byval arguments
 commit | commitdiff | tree
2013-10-13 Vincent LejeuneR600: Use masked read sel for texture instructions
 commit | commitdiff | tree
2013-10-13 Vincent LejeuneR600: fix swizzle export
 commit | commitdiff | tree
2013-10-13 Vincent LejeuneR600: Clear the VPM bit of export instructions.
 commit | commitdiff | tree
2013-10-02 Vincent LejeuneR600: Add a ldptr intrinsic to support MSAA.
 commit | commitdiff | tree
2013-10-01 Vincent LejeuneR600: add a pass that merges clauses.
 commit | commitdiff | tree
2013-10-01 Vincent LejeuneR600: Put PRED_X instruction in its own clause
 commit | commitdiff | tree
2013-10-01 Vincent LejeuneR600: Enable -verify-machineinstrs in some tests.
 commit | commitdiff | tree
2013-09-12 Vincent LejeuneR600: Move clamp handling code to R600IselLowering.cpp
 commit | commitdiff | tree
2013-09-12 Vincent LejeuneR600: Move code handling literal folding into R600ISelLowering.
 commit | commitdiff | tree
2013-09-12 Vincent LejeuneR600: Move fabs/fneg/sel folding logic into PostProcessIsel
 commit | commitdiff | tree
2013-09-04 Vincent LejeuneR600: Use shared op optimization when checking cycle...
commit | commitdiff | tree
2013-09-04 Vincent LejeuneR600: Non vector only instruction can be scheduled...
commit | commitdiff | tree
2013-09-04 Vincent LejeuneR600: Use SchedModel enum for is{Trans,Vector}Only...
commit | commitdiff | tree
2013-09-04 Vincent LejeuneR600: Remove fmul.v4f32.ll test which is redundant...
commit | commitdiff | tree
2013-09-03 Vincent LejeuneTableGen: Enumerate Schedule Model too.
 commit | commitdiff | tree
2013-07-31 Vincent LejeuneR600: Do not mergevector after a vector reg is used
 commit | commitdiff | tree
2013-07-31 Vincent LejeuneR600: Avoid more than 4 literals in the same instruction...
commit | commitdiff | tree
2013-07-31 Vincent LejeuneR600: Non vector only instruction can be scheduled...
commit | commitdiff | tree
2013-07-31 Vincent LejeuneR600: Don't mix LDS and non-LDS instructions in the...
commit | commitdiff | tree
2013-07-31 Vincent LejeuneR600: Use SchedModel enum for is{Trans,Vector}Only...
commit | commitdiff | tree
2013-07-31 Vincent LejeuneTableGen: Enumerate Schedule Model too.
 commit | commitdiff | tree
2013-07-31 Vincent LejeuneR600: Remove predicated_break inst
 commit | commitdiff | tree
2013-07-19 Vincent LejeuneR600: Don't emit empty then clause and use alu_pop_after
 commit | commitdiff | tree
2013-07-19 Vincent LejeuneR600: Simplify AMDILCFGStructurize by removing templates...
commit | commitdiff | tree
2013-07-19 Vincent LejeuneR600: Replace legacy debug code in AMDILCFGStructurizer.cpp
 commit | commitdiff | tree
2013-07-09 Vincent LejeuneR600: Do not predicated basic block with multiple alu...
commit | commitdiff | tree
2013-07-09 Vincent LejeuneR600: Fix a rare bug where swizzle optimization returns...
commit | commitdiff | tree
2013-07-09 Vincent LejeuneR600: Fix wrong export reswizzling
 commit | commitdiff | tree
2013-07-09 Vincent LejeuneR600: Use DAG lowering pass to handle fcos/fsin
 commit | commitdiff | tree
2013-07-09 Vincent LejeuneR600: Print Export Swizzle
 commit | commitdiff | tree
2013-06-30 Vincent LejeuneR600: Fix an unitialized variable in R600InstrInfo.cpp
 commit | commitdiff | tree
2013-06-29 Vincent LejeuneR600: Support schedule and packetization of trans-only...
commit | commitdiff | tree
2013-06-29 Vincent LejeuneR600: Bank Swizzle now display SCL equivalent
 commit | commitdiff | tree
2013-06-17 Vincent LejeuneR600: PV stores Reg id, not index
 commit | commitdiff | tree
2013-06-17 Vincent LejeuneR600: Properly set COUNT_3 bit in TEX clause initiating...
commit | commitdiff | tree
2013-06-07 Vincent LejeuneR600: Use a refined heuristic to choose when switching...
commit | commitdiff | tree
2013-06-07 Vincent LejeuneR600: Anti dep better handled in tex clause
 commit | commitdiff | tree
2013-06-07 Vincent LejeuneR600: Remove an extra break in R600OptimizeVectorRegisters.cpp
 commit | commitdiff | tree
2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler
 commit | commitdiff | tree
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp
 commit | commitdiff | tree
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
 commit | commitdiff | tree
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
commit | commitdiff | tree
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
 commit | commitdiff | tree
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
 commit | commitdiff | tree
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
 commit | commitdiff | tree
2013-06-04 Vincent LejeuneR600: Add a test for r183108
 commit | commitdiff | tree
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the result...
commit | commitdiff | tree
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
 commit | commitdiff | tree
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
 commit | commitdiff | tree
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Lower int_load_input to copyFromReg instead of...
commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Use bottom up scheduling algorithm
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Use depth first scheduling algorithm
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Replace big texture opcode switch in scheduler...
commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Relax some vector constraints on Dot4.
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Improve texture handling
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Rename 128 bit registers.
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Some factorization
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: Factorize Fetch size limit inside AMDGPUSubTarget
 commit | commitdiff | tree
2013-05-17 Vincent LejeuneR600: prettier dump of clamp
 commit | commitdiff | tree
2013-05-02 Vincent LejeuneR600: Signed literals are 64bits wide
 commit | commitdiff | tree
2013-05-02 Vincent LejeuneR600: If previous bundle is dot4, PV valid chan is...
commit | commitdiff | tree
2013-05-02 Vincent LejeuneR600: Add a test to check that use_kill is emitted
 commit | commitdiff | tree
2013-05-02 Vincent LejeuneR600: Improve asmPrint of ALU clause
 commit | commitdiff | tree
2013-05-02 Vincent LejeuneR600: Prettier asmPrint of Alu
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: fix loop-address.ll test
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Always use texture cache for compute shaders
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: use native for alu
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Packetize instructions
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Rework Scheduling to handle difference between...
commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Add a Bank Swizzle operand
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Take inner dependency into tex/vtx clauses
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Turn TEX/VTX into native instructions
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Add FetchInst bit to instruction defs to denote...
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache...
commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Add some new processor variants
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: Clean up instruction class definitions
 commit | commitdiff | tree
2013-04-30 Vincent LejeuneR600: config section now reports use of killgt
 commit | commitdiff | tree
2013-04-23 Vincent LejeuneR600: Use .AMDGPU.config section to emit stacksize
 commit | commitdiff | tree
2013-04-23 Vincent LejeuneR600: Add CF_END
 commit | commitdiff | tree
2013-04-17 Vincent LejeuneR600: Make Export Instruction not duplicable
 commit | commitdiff | tree
2013-04-17 Vincent LejeuneR600: Export is emitted as a CF_NATIVE inst
 commit | commitdiff | tree
2013-04-17 Vincent LejeuneR600: Emit used GPRs count
 commit | commitdiff | tree
2013-04-10 Vincent LejeuneR600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when...
commit | commitdiff | tree
2013-04-08 Vincent LejeuneR600: Control Flow support for pre EG gen
 commit | commitdiff | tree
next
C/C++ LLVM-based compilers that forbids OOTA behaviors