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oota-llvm.git
2013-06-07
Benjamin Kramer
Optimize BitVector::all().
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2013-06-07
Benjamin Kramer
Fold variable that's only used in assert into the assert.
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2013-06-07
Bill Wendling
Add a script to help us create source tar balls for...
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2013-06-07
Bill Wendling
Use proper exit code.
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2013-06-07
Duncan Sands
Correct wrong register in this example, pointed out...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-07
Michael Gottesman
[objc-arc] Ensure that the cfg path count does not...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-07
Bill Wendling
Don't cache the instruction info and register info...
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2013-06-07
Manman Ren
DIBuilder: No functionality change.
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2013-06-07
Arnold Schwaighofer
ARM sched model: Use the right resources for DIV
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2013-06-07
Arnold Schwaighofer
ARM sched model: Add VFP div instruction on Swift
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2013-06-07
Arnold Schwaighofer
CodeGenSchedule: Use resize instead of copying a vector
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2013-06-07
Arnold Schwaighofer
ARM sched model: Add SIMD/VFP load/store instructions...
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2013-06-07
Venkatraman...
[Sparc]: Use cmp instruction instead of subcc to compar...
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2013-06-06
Jakub Staszak
Simplify code. No functionality change.
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2013-06-06
Jakub Staszak
Remove unneeded #include.
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2013-06-06
Arnold Schwaighofer
CodeGenSchedule: smallvector.push_back(smallvector...
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2013-06-06
Vincent Lejeune
R600: Rewrite an awkward loop in R600MachineScheduler
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2013-06-06
Nadav Rotem
Jeffrey Yasskin volunteered to benchmark the vectorizer...
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2013-06-06
David Blaikie
Fix break in r183446 - helps to increment the iterator...
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2013-06-06
Arnold Schwaighofer
Revert "ARM sched model: Add SIMD/VFP load/store instru...
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2013-06-06
David Blaikie
Debug Info: simplify parameter ordering preservation
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add SIMD/VFP load/store instructions...
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2013-06-06
Kevin Enderby
Move the test for the data in code into the ARM directo...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add integer VFP/SIMD instructions...
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2013-06-06
Jakub Staszak
Re-apply "Use IRBuilder instead of ConstantInt methods...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add integer load/store instructions...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add integer arithmetic instructions...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Cortex A9 - More InstRW sched resources
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2013-06-06
Rafael Espindola
Add a testcase from pr16244.
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add branch thumb instructions
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add branch thumb2 instructions
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add branch instructions
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add preload thumb2 instructions
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2013-06-06
Jakub Staszak
Remove unimplemented definition. Found using [-Wunused...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add preload instructions
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2013-06-06
Kevin Enderby
Teach llvm-objdump with the -macho parser how to use...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add more ALU and CMP thumb instructions
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2013-06-06
Rafael Espindola
Revert "Use IRBuilder instead of ConstantInt methods...
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2013-06-06
Arnold Schwaighofer
ARM sched model: Add more ALU and CMP thumb2 instructions
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2013-06-06
Vincent Lejeune
R600: Remove leftover code in R600MachineScheduler.cpp
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2013-06-06
Rafael Espindola
Print symbol names in relocations when dumping COFF...
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2013-06-06
Bill Wendling
Cast to the correct type. Pointer, not reference.
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2013-06-06
NAKAMURA Takumi
R600OptimizeVectorRegisters.cpp: Tweak a warning. ...
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2013-06-06
NAKAMURA Takumi
R600OptimizeVectorRegisters.cpp: Suppress a warning...
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2013-06-06
NAKAMURA Takumi
Trailing linefeed.
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2013-06-06
Bill Wendling
Cast to the proper type.
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2013-06-06
Jakub Staszak
Remove unneeded cast<>.
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2013-06-06
Sean Silva
Add some class documentation to BinaryRef.
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2013-06-06
Bill Wendling
Cache the TargetLowering info object as a pointer.
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2013-06-06
Jakub Staszak
Use IRBuilder instead of ConstantInt methods.
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2013-06-06
Bill Wendling
Don't cache the TargetLoweringInfo object inside of...
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2013-06-05
Sean Silva
Rename operator== parameter to `RHS`.
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2013-06-05
Sean Silva
Remove error-prone methods of BinaryRef.
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2013-06-05
Sean Silva
Add writeAsHex(raw_ostream &) method to BinaryRef.
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2013-06-05
Tom Stellard
R600: Replace predicate loop with predicate function
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2013-06-05
Sean Silva
Rename BinaryRef::isBinary to more descriptive DataIsHe...
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2013-06-05
Sean Silva
Add BinaryRef binary_size() method.
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2013-06-05
Sean Silva
Comment BinaryRef::Data.
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2013-06-05
Bill Wendling
Add space to assert message.
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2013-06-05
Sean Silva
Add writeAsBinary(raw_ostream &) method to BinaryRef.
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2013-06-05
Vincent Lejeune
R600: Add a pass that merge Vector Register
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2013-06-05
Sean Silva
[docs] Add link to C++ ABI document.
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2013-06-05
Sean Silva
[docs] Add link to SysV ABI document.
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2013-06-05
Sean Silva
[ELF] Add ELFOSABI_GNU.
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2013-06-05
Rafael Espindola
Don't hide the first ELF symbol.
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2013-06-05
Vincent Lejeune
R600: Schedule copy from phys register at beginning...
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2013-06-05
Sean Silva
yaml2obj: split out COFF logic into separate file
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2013-06-05
Akira Hatanaka
[mips] brcond + setgt/setugt instruction selection...
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2013-06-05
Sean Silva
yaml2obj: add -format=<fmt> to choose input YAML interp...
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2013-06-05
Jakub Staszak
Use IRBuilder instead of ConstantInt methods. It simpli...
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2013-06-05
Michael Liao
[PATCH] Fix VGATHER* operand constraints
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2013-06-05
Rafael Espindola
Represent symbols with a SymbolIndex,SectionIndex pair.
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2013-06-05
Arnold Schwaighofer
ARM sched model: Add more ALU and CMP instructions
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2013-06-05
Arnold Schwaighofer
ARM sched model: Add divsion, loads, branches, vfp cvt
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2013-06-05
Arnold Schwaighofer
ARMInstrInfo: Improve isSwiftFastImmShift
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2013-06-05
Arnold Schwaighofer
SubtargetEmitter fix
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2013-06-05
Mihai Popa
This is a simple patch that changes RRX and RRXS to...
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2013-06-05
Sylvestre Ledru
The GNU/HURD is also using the libc. Therefor, endian...
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2013-06-05
Andrew Trick
Fix a tblgen subtargetemitter bug, for future Swift...
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2013-06-05
David Blaikie
PR15662: Optimized debug info produces out of order...
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2013-06-05
Tom Stellard
R600: Make sure to schedule AR register uses and defs...
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2013-06-05
Rafael Espindola
Don't print default values for NumberOfAuxSymbols and...
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2013-06-05
Rafael Espindola
Handle (at least don't crash on) relocations with no...
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2013-06-05
Rafael Espindola
Move BinaryRef to a new include/llvm/Object/YAML.h...
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2013-06-05
Rafael Espindola
Revert "R600: Add a pass that merge Vector Register"
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2013-06-05
Rafael Espindola
Handle relocations that don't point to symbols.
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2013-06-04
Sean Silva
[docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE(...
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2013-06-04
Vincent Lejeune
R600: Add a pass that merge Vector Register
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2013-06-04
Vincent Lejeune
R600: Const/Neg/Abs can be folded to dot4
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2013-06-04
Evan Cheng
Cortex-R5 can issue Thumb2 integer division instructions.
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2013-06-04
Arnold Schwaighofer
Revert series of sched model patches until I figure...
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2013-06-04
Arnold Schwaighofer
ARM sched model: Add VFP div instruction on Swift
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2013-06-04
Arnold Schwaighofer
ARM sched model: Add SIMD/VFP load/store instructions...
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2013-06-04
Arnold Schwaighofer
ARM sched model: Add integer VFP/SIMD instructions...
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