2013-06-06 |
Jakub Staszak | Remove unneeded cast<>. |
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2013-06-06 |
Sean Silva | Add some class documentation to BinaryRef. |
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2013-06-06 |
Bill Wendling | Cache the TargetLowering info object as a pointer. |
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2013-06-06 |
Jakub Staszak | Use IRBuilder instead of ConstantInt methods. |
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2013-06-06 |
Bill Wendling | Don't cache the TargetLoweringInfo object inside of... |
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2013-06-05 |
Sean Silva | Rename operator== parameter to `RHS`. |
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2013-06-05 |
Sean Silva | Remove error-prone methods of BinaryRef. |
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2013-06-05 |
Sean Silva | Add writeAsHex(raw_ostream &) method to BinaryRef. |
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2013-06-05 |
Tom Stellard | R600: Replace predicate loop with predicate function |
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2013-06-05 |
Sean Silva | Rename BinaryRef::isBinary to more descriptive DataIsHe... |
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2013-06-05 |
Sean Silva | Add BinaryRef binary_size() method. |
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2013-06-05 |
Sean Silva | Comment BinaryRef::Data. |
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2013-06-05 |
Bill Wendling | Add space to assert message. |
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2013-06-05 |
Sean Silva | Add writeAsBinary(raw_ostream &) method to BinaryRef. |
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2013-06-05 |
Vincent Lejeune | R600: Add a pass that merge Vector Register |
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2013-06-05 |
Sean Silva | [docs] Add link to C++ ABI document. |
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2013-06-05 |
Sean Silva | [docs] Add link to SysV ABI document. |
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2013-06-05 |
Sean Silva | [ELF] Add ELFOSABI_GNU. |
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2013-06-05 |
Rafael Espindola | Don't hide the first ELF symbol. |
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2013-06-05 |
Vincent Lejeune | R600: Schedule copy from phys register at beginning... |
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2013-06-05 |
Sean Silva | yaml2obj: split out COFF logic into separate file |
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2013-06-05 |
Akira Hatanaka | [mips] brcond + setgt/setugt instruction selection... |
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2013-06-05 |
Sean Silva | yaml2obj: add -format=<fmt> to choose input YAML interp... |
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2013-06-05 |
Jakub Staszak | Use IRBuilder instead of ConstantInt methods. It simpli... |
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2013-06-05 |
Michael Liao | [PATCH] Fix VGATHER* operand constraints |
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2013-06-05 |
Rafael Espindola | Represent symbols with a SymbolIndex,SectionIndex pair. |
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2013-06-05 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP instructions |
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2013-06-05 |
Arnold Schwaighofer | ARM sched model: Add divsion, loads, branches, vfp cvt |
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2013-06-05 |
Arnold Schwaighofer | ARMInstrInfo: Improve isSwiftFastImmShift |
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2013-06-05 |
Arnold Schwaighofer | SubtargetEmitter fix |
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2013-06-05 |
Mihai Popa | This is a simple patch that changes RRX and RRXS to... |
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2013-06-05 |
Sylvestre Ledru | The GNU/HURD is also using the libc. Therefor, endian... |
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2013-06-05 |
Andrew Trick | Fix a tblgen subtargetemitter bug, for future Swift... |
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2013-06-05 |
David Blaikie | PR15662: Optimized debug info produces out of order... |
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2013-06-05 |
Tom Stellard | R600: Make sure to schedule AR register uses and defs... |
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2013-06-05 |
Rafael Espindola | Don't print default values for NumberOfAuxSymbols and... |
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2013-06-05 |
Rafael Espindola | Handle (at least don't crash on) relocations with no... |
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2013-06-05 |
Rafael Espindola | Move BinaryRef to a new include/llvm/Object/YAML.h... |
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2013-06-05 |
Rafael Espindola | Revert "R600: Add a pass that merge Vector Register" |
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2013-06-05 |
Rafael Espindola | Handle relocations that don't point to symbols. |
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2013-06-04 |
Sean Silva | [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE(... |
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2013-06-04 |
Vincent Lejeune | R600: Add a pass that merge Vector Register |
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2013-06-04 |
Vincent Lejeune | R600: Const/Neg/Abs can be folded to dot4 |
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2013-06-04 |
Evan Cheng | Cortex-R5 can issue Thumb2 integer division instructions. |
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2013-06-04 |
Arnold Schwaighofer | Revert series of sched model patches until I figure... |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add VFP div instruction on Swift |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add SIMD/VFP load/store instructions... |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer VFP/SIMD instructions... |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer load/store instructions... |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer arithmetic instructions... |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Cortex A9 - More InstRW sched resources |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch thumb instructions |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch thumb2 instructions |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch instructions |
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2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add preload thumb2 instructions |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add preload instructions |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb instructions |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb2 instructions |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP instructions |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add divsion, loads, branches, vfp cvt |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | ARMInstrInfo: Improve isSwiftFastImmShift |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Arnold Schwaighofer | SubtargetEmitter fix |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Richard Smith | Fix link. |
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2013-06-04 |
Venkatraman... | Sparc: No functionality change. Cleanup whitespaces... |
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2013-06-04 |
David Majnemer | IndVarSimplify: check if loop invariant expansion can... |
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2013-06-04 |
David Majnemer | ARM: Fix crash in ARM backend inside of ARMConstantIsla... |
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2013-06-04 |
Bob Wilson | Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options. |
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2013-06-04 |
Vincent Lejeune | R600: Swizzle texture/export instructions |
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2013-06-04 |
Vincent Lejeune | R600: Add a test for r183108 |
commit | commitdiff | tree | snapshot |
2013-06-04 |
Rafael Espindola | Second part of pr16069 |
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2013-06-04 |
Hans Wennborg | Typo: s/caes/cases/ in SimplifyCFG |
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2013-06-04 |
Benjamin Kramer | Preserve const correctness. |
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2013-06-04 |
Vladimir Medic | Test commit for user vmedic, to verify commit access... |
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2013-06-04 |
Alexey Samsonov | [llvm-symbolizer] Avoid calling slow getSymbolSize... |
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2013-06-04 |
Bill Wendling | We are now in 3.4 land. We don't need the 3.3 releaese... |
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2013-06-04 |
Michael Gottesman | IEEE-754R 5.7.2 General Operations is* operations ... |
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2013-06-04 |
Aaron Ballman | Silencing an MSVC warning about mixing bool and unsigne... |
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2013-06-04 |
Aaron Ballman | Silencing an MSVC warning about */ being found outside... |
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2013-06-04 |
Shuxin Yang | Fix a defect in code-layout pass, improving Benchmarks... |
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2013-06-03 |
Nick Lewycky | Delete dead safety check. |
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2013-06-03 |
David Majnemer | SimplifyCFG: Do not transform PHI to select if doing... |
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2013-06-03 |
David Majnemer | SimplifyCFG: Small cleanup, use ICmpInst::isEquality() |
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2013-06-03 |
Rafael Espindola | Remove dead code. |
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2013-06-03 |
Rafael Espindola | Update RuntimeDyldELF::findOPDEntrySection the new... |
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2013-06-03 |
Rafael Espindola | Enable mcjit tests on ppc64 when building with cmake. |
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2013-06-03 |
Tom Stellard | R600/SI: Add support for work item and work group intri... |
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2013-06-03 |
Tom Stellard | R600/SI: Add a calling convention for compute shaders |
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2013-06-03 |
Tom Stellard | R600/SI: Custom lower i64 sign_extend |
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2013-06-03 |
Tom Stellard | R600/SI: Adjust some instructions' out register class... |
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2013-06-03 |
Tom Stellard | R600/SI: Handle REG_SEQUENCE in fitsRegClass() |
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2013-06-03 |
Tom Stellard | R600/SI: Handle nodes with glue results correctly SITar... |
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2013-06-03 |
Tom Stellard | R600/SI: Fixup CopyToReg register class in PostprocessI... |
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2013-06-03 |
Tom Stellard | R600/SI: Add support for global loads |
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2013-06-03 |
Tom Stellard | R600/SI: Rework MUBUF store instructions |
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2013-06-03 |
Vincent Lejeune | R600: 3 op instructions have no write bit but the resul... |
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2013-06-03 |
Vincent Lejeune | R600: CALL_FS consumes a stack size entry |
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2013-06-03 |
Vincent Lejeune | R600: use capital letter for PV channel |
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2013-06-03 |
Vincent Lejeune | R600: Constraints input regs of interp_xy,_zw |
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2013-06-03 |
Kostya Serebryany | [asan] ASan Linux MIPS32 support (llvm part), patch... |
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2013-06-03 |
Ahmed Bougacha | X86: sub_xmm registers are 128 bits wide. |
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