oota-llvm.git
2013-06-07 Quentin ColombetTeach AsmPrinter how to print odd constants.
2013-06-07 Manman RenDIBuilder: No functionality change.
2013-06-07 Benjamin KramerVincent says the element is at most once in the vector...
2013-06-07 Rafael EspindolaUse isxdigit.
2013-06-07 Rafael EspindolaMake operator== non-member for greater symmetry.
2013-06-07 Roman DivackyFix a typo in asm string of BP* family of instructions...
2013-06-07 Rui Ueyama[Object/COFF] BaseOfData field should be absent in...
2013-06-07 Rafael EspindolaSupport OpenBSD's native frame protection conventions.
2013-06-07 Benjamin KramerR600: Fix a potential iterator invalidation issue.
2013-06-07 Vincent LejeuneR600: Remove an extra break in R600OptimizeVectorRegist...
2013-06-07 Alexey Samsonov[llvm-symbolizer] rewrite r183213 in a more clear way
2013-06-07 Benjamin KramerBitVector: Do the right thing in all() when Size is...
2013-06-07 Benjamin KramerOptimize BitVector::all().
2013-06-07 Benjamin KramerFold variable that's only used in assert into the assert.
2013-06-07 Bill WendlingAdd a script to help us create source tar balls for...
2013-06-07 Bill WendlingUse proper exit code.
2013-06-07 Duncan SandsCorrect wrong register in this example, pointed out...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Michael Gottesman[objc-arc] Ensure that the cfg path count does not...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction info and register info...
2013-06-07 Manman RenDIBuilder: No functionality change.
2013-06-07 Arnold SchwaighoferARM sched model: Use the right resources for DIV
2013-06-07 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-07 Arnold SchwaighoferCodeGenSchedule: Use resize instead of copying a vector
2013-06-07 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-07 Venkatraman... [Sparc]: Use cmp instruction instead of subcc to compar...
2013-06-06 Jakub StaszakSimplify code. No functionality change.
2013-06-06 Jakub StaszakRemove unneeded #include.
2013-06-06 Arnold SchwaighoferCodeGenSchedule: smallvector.push_back(smallvector...
2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler
2013-06-06 Nadav RotemJeffrey Yasskin volunteered to benchmark the vectorizer...
2013-06-06 David BlaikieFix break in r183446 - helps to increment the iterator...
2013-06-06 Arnold SchwaighoferRevert "ARM sched model: Add SIMD/VFP load/store instru...
2013-06-06 David BlaikieDebug Info: simplify parameter ordering preservation
2013-06-06 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-06 Kevin EnderbyMove the test for the data in code into the ARM directo...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-06 Jakub StaszakRe-apply "Use IRBuilder instead of ConstantInt methods...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-06 Rafael EspindolaAdd a testcase from pr16244.
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-06 Jakub StaszakRemove unimplemented definition. Found using [-Wunused...
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-06 Kevin EnderbyTeach llvm-objdump with the -macho parser how to use...
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-06 Rafael EspindolaRevert "Use IRBuilder instead of ConstantInt methods...
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp
2013-06-06 Rafael EspindolaPrint symbol names in relocations when dumping COFF...
2013-06-06 Bill WendlingCast to the correct type. Pointer, not reference.
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Tweak a warning. ...
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Suppress a warning...
2013-06-06 NAKAMURA TakumiTrailing linefeed.
2013-06-06 Bill WendlingCast to the proper type.
2013-06-06 Jakub StaszakRemove unneeded cast<>.
2013-06-06 Sean SilvaAdd some class documentation to BinaryRef.
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer.
2013-06-06 Jakub StaszakUse IRBuilder instead of ConstantInt methods.
2013-06-06 Bill WendlingDon't cache the TargetLoweringInfo object inside of...
2013-06-05 Sean SilvaRename operator== parameter to `RHS`.
2013-06-05 Sean SilvaRemove error-prone methods of BinaryRef.
2013-06-05 Sean SilvaAdd writeAsHex(raw_ostream &) method to BinaryRef.
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function
2013-06-05 Sean SilvaRename BinaryRef::isBinary to more descriptive DataIsHe...
2013-06-05 Sean SilvaAdd BinaryRef binary_size() method.
2013-06-05 Sean SilvaComment BinaryRef::Data.
2013-06-05 Bill WendlingAdd space to assert message.
2013-06-05 Sean SilvaAdd writeAsBinary(raw_ostream &) method to BinaryRef.
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-05 Sean Silva[docs] Add link to C++ ABI document.
2013-06-05 Sean Silva[docs] Add link to SysV ABI document.
2013-06-05 Sean Silva[ELF] Add ELFOSABI_GNU.
2013-06-05 Rafael EspindolaDon't hide the first ELF symbol.
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
2013-06-05 Sean Silvayaml2obj: split out COFF logic into separate file
2013-06-05 Akira Hatanaka[mips] brcond + setgt/setugt instruction selection...
2013-06-05 Sean Silvayaml2obj: add -format=<fmt> to choose input YAML interp...
2013-06-05 Jakub StaszakUse IRBuilder instead of ConstantInt methods. It simpli...
2013-06-05 Michael Liao[PATCH] Fix VGATHER* operand constraints
2013-06-05 Rafael EspindolaRepresent symbols with a SymbolIndex,SectionIndex pair.
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-05 Arnold SchwaighoferSubtargetEmitter fix
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to...
2013-06-05 Sylvestre LedruThe GNU/HURD is also using the libc. Therefor, endian...
2013-06-05 Andrew TrickFix a tblgen subtargetemitter bug, for future Swift...
2013-06-05 David BlaikiePR15662: Optimized debug info produces out of order...
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
2013-06-05 Rafael EspindolaDon't print default values for NumberOfAuxSymbols and...
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