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clk: rockchip: optimizing ddrclk_scpi_recalc_rate behavior
authorTang Yun ping <typ@rock-chips.com>
Thu, 6 Apr 2017 07:25:12 +0000 (15:25 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 7 Apr 2017 02:15:55 +0000 (10:15 +0800)
commit3e6193627508f100fe58a289683f8ef44eef66eb
tree1b03f4a361841393b8cb791c725b7cc6b52cdcb3tree | snapshot
parent6168e92bdd527b4cd8bc1f0125611e9fcc361695commit | diff
clk: rockchip: optimizing ddrclk_scpi_recalc_rate behavior

Cat ddr frequency from rockchip_ddrclk_scpi_set_rate prior to
rockchip_ddrclk_scpi_recalc_rate, to optimizing running time and reduce
SCPI APIs usage rate.

Change-Id: Iba31d33a5920816b1cc230f639ea3a9503d451c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
drivers/clk/rockchip/clk-ddr.c diff | blob | history
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