arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/wakeup_reason.h>
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #define CPU 3288
  25 //#include "sram.h"
  26 #include "pm-pie.c"
  27
  28 __weak void rk_usb_power_down(void);
  29 __weak void rk_usb_power_up(void);
  30
  31 //static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
  32 //static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
  33 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
  34
  35 /*************************cru define********************************************/
  36
  37
  38 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  39 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  40
  41 enum rk_plls_id {
  42         APLL_ID = 0,
  43         DPLL_ID,
  44         CPLL_ID,
  45         GPLL_ID,
  46         NPLL_ID,
  47         END_PLL_ID,
  48 };
  49
  50 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
  51 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
  52 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
  53
  54
  55 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
  56 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
  57
  58 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
  59 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
  60 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
  61
  62 /*******************************gpio define **********************************************/
  63
  64 /* GPIO control registers */
  65 #define GPIO_SWPORT_DR          0x00
  66 #define GPIO_SWPORT_DDR         0x04
  67 #define GPIO_INTEN                      0x30
  68 #define GPIO_INTMASK            0x34
  69 #define GPIO_INTTYPE_LEVEL      0x38
  70 #define GPIO_INT_POLARITY       0x3c
  71 #define GPIO_INT_STATUS         0x40
  72 #define GPIO_INT_RAWSTATUS      0x44
  73 #define GPIO_DEBOUNCE           0x48
  74 #define GPIO_PORTS_EOI          0x4c
  75 #define GPIO_EXT_PORT           0x50
  76 #define GPIO_LS_SYNC            0x60
  77
  78 /***********************************sleep func*********************************************/
  79
  80 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
  81 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
  82 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
  83
  84 // sys resume code in boot ram
  85 #define  RKPM_BOOT_CODE_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
  86 #define  RKPM_BOOT_CODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
  87
  88
  89 // sys resume data in boot ram
  90 #define  RKPM_BOOT_DATA_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
  91 #define  RKPM_BOOT_DATA_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
  92
  93 // ddr resume data in boot ram
  94 #define  RKPM_BOOT_DDRCODE_PHY   (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
  95 #define  RKPM_BOOT_DDRCODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
  96
  97 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
  98
  99 // the value is used to control cpu resume flow
 100 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
 101 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
 102 static char *resume_data_phy=  (char *)( RKPM_BOOT_DATA_PHY);
 103
 104
 105
 106 #define BOOT_RAM_SIZE   (4*1024)
 107 #define INT_RAM_SIZE            (64*1024)
 108
 109 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
 110 static char int_ram_data[INT_RAM_SIZE];
 111
 112 char * ddr_get_resume_code_info(u32 *size);
 113 char * ddr_get_resume_data_info(u32 *size);
 114
 115 /**
 116 ddr code and data
 117
 118 *** code start
 119 ---data offset--
 120 ---code----
 121 ---data----
 122 */
 123 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
 124 {
 125
 126         char *addr_base,*addr_phy,*data_src,*data_dst;
 127         u32 sr_size,data_size;
 128
 129         addr_base=(char *)RKPM_BOOTRAM_BASE;
 130         addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 131         sr_size=RKPM_BOOTRAM_SIZE;
 132
 133         // save boot sram
 134          if(boot_save)
 135                  memcpy(boot_save,addr_base, sr_size);
 136
 137         // move resume code and date to boot sram
 138         // move sys code
 139         data_dst=(char *)RKPM_BOOT_CODE_BASE;
 140         data_src=(char *)rkpm_slp_cpu_resume;
 141         data_size=RKPM_BOOT_CODE_SIZE;
 142         memcpy((char *)data_dst,(char *)data_src, data_size);
 143
 144         // move sys data
 145         data_dst=(char *)resume_data_base;
 146         data_src=(char *)sleep_resume_data;
 147         data_size=sizeof(sleep_resume_data);
 148         memcpy((char *)data_dst,(char *)data_src, data_size);
 149
 150         if(flag)
 151         {
 152                 /*************************ddr code cpy*************************************/
 153                 // ddr code
 154                 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
 155                 data_src=(char *)ddr_get_resume_code_info(&data_size);
 156
 157                 data_size=RKPM_ALIGN(data_size,4);
 158
 159                 memcpy((char *)data_dst,(char *)data_src, data_size);
 160
 161                 // ddr data
 162                 data_dst=(char *)(data_dst+data_size);
 163
 164                 data_src=(char *)ddr_get_resume_data_info(&data_size);
 165                 data_size=RKPM_ALIGN(data_size,4);
 166                 memcpy((char *)data_dst,(char *)data_src, data_size);
 167
 168                 /*************************ddr code cpy  end*************************************/
 169                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 170                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 171                 /*************************int mem bak*************************************/
 172                 // int mem
 173                 addr_base=(char *)rockchip_sram_virt;
 174                 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 175                 sr_size=rockchip_sram_size;
 176                 //  rkpm_ddr_printascii("piephy\n");
 177                 //rkpm_ddr_printhex(addr_phy);
 178                 //mmap
 179                 if(int_save)
 180                     memcpy(int_save,addr_base, sr_size);
 181
 182                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 183                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 184         }
 185
 186  }
 187
 188 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
 189 {
 190
 191     char *addr_base,*addr_phy;
 192     u32 sr_size;
 193
 194     addr_base=(char *)RKPM_BOOTRAM_BASE;
 195     addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 196     sr_size=RKPM_BOOTRAM_SIZE;
 197     // save boot sram
 198     if(boot_save)
 199         memcpy(addr_base,boot_save, sr_size);
 200
 201     flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 202     outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
 203
 204     if(flag)
 205     {
 206         // int mem
 207         addr_base=(char *)rockchip_sram_virt;
 208         addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 209         sr_size=rockchip_sram_size;
 210
 211         if(int_save)
 212         memcpy(addr_base, int_save,sr_size);
 213
 214         flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 215         outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
 216      }
 217 }
 218
 219 /**************************************gic save and resume**************************/
 220 #define  RK_GICD_BASE (RK_GIC_VIRT)
 221 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
 222
 223 #define PM_IRQN_START 32
 224 #define PM_IRQN_END     107//107
 225 #if 0 //funciton is ok ,but not used
 226 static void pm_gic_enable(u32 irqs)
 227 {
 228
 229         int irqstart=0;
 230         u32 bit_off;
 231         void __iomem *reg_off;
 232         unsigned int gic_irqs;
 233
 234         gic_irqs = PM_IRQN_END;
 235         irqstart=PM_IRQN_START;//PM_IRQN_START;
 236
 237         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
 238         bit_off=irqs%32;
 239         writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
 240
 241         dsb();
 242 }
 243
 244 static void rkpm_gic_disable(u32 irqs)
 245 {
 246         int irqstart=0;
 247         u32 bit_off;
 248         void __iomem *reg_off;
 249         unsigned int gic_irqs;
 250
 251         gic_irqs = PM_IRQN_END;
 252         irqstart=PM_IRQN_START;//PM_IRQN_START;
 253
 254         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
 255         bit_off=irqs%32;
 256         writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
 257         dsb();
 258 }
 259 #endif
 260 #define gic_reg_dump(a,b,c)  {}//reg_dump((a),(b),(c))
 261
 262 static u32 slp_gic_save[260+50];
 263
 264
 265 static void rkpm_gic_dist_save(u32 *context)
 266 {
 267      int i = 0,j,irqstart=0;
 268      unsigned int gic_irqs;
 269
 270      gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 271      gic_irqs = (gic_irqs + 1) * 32;
 272      if (gic_irqs > 1020)
 273      gic_irqs = 1020;
 274      //printk("gic_irqs=%d\n",gic_irqs);
 275      //gic_irqs = PM_IRQN_END;
 276      irqstart=PM_IRQN_START;//PM_IRQN_START;
 277
 278      i = 0;
 279      //level
 280      for (j = irqstart; j < gic_irqs; j += 16)
 281       context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
 282      gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 283
 284      /*
 285      * Set all global interrupts to this CPU only.
 286      */
 287      for(j = 0; j < gic_irqs; j += 4)
 288          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET +    (j * 4) / 4);
 289      gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
 290
 291      //pri
 292      for (j = 0; j < gic_irqs; j += 4)
 293          context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 294      gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 295
 296      //secure
 297      for (j = 0; j < gic_irqs; j += 32)
 298          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4) / 32);
 299      gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
 300
 301      for (j = irqstart; j < gic_irqs; j += 32)
 302          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
 303      gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 304
 305     #if 0
 306      //disable
 307      for (j = 0; j < gic_irqs; j += 32)
 308          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
 309      gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 310     #endif
 311
 312      //enable
 313      for (j = 0; j < gic_irqs; j += 32)
 314          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 315      gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 316
 317
 318
 319      gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 320      gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 321
 322      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 323      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 324      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 325
 326     #if 0
 327      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 328      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 329      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 330      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 331      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 332     #endif
 333
 334     #if 1
 335     for (j = irqstart; j < gic_irqs; j += 32)
 336     {
 337         writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 338         dsb();
 339     }
 340     writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 341     writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 342
 343     writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
 344     writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
 345     #endif
 346
 347 }
 348
 349 static void rkpm_gic_dist_resume(u32 *context)
 350 {
 351
 352          int i = 0,j,irqstart=0;
 353          unsigned int gic_irqs;
 354
 355
 356          gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 357          gic_irqs = (gic_irqs + 1) * 32;
 358          if (gic_irqs > 1020)
 359                  gic_irqs = 1020;
 360
 361          //gic_irqs = PM_IRQN_END;
 362          irqstart=PM_IRQN_START;//PM_IRQN_START;
 363
 364          writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
 365          dsb();
 366          writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
 367          dsb();
 368          for (j = irqstart; j < gic_irqs; j += 32)
 369          {
 370                  writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 371                  dsb();
 372          }
 373
 374          i = 0;
 375
 376          //trig
 377          for (j = irqstart; j < gic_irqs; j += 16)
 378          {
 379                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
 380                  dsb();
 381          }
 382          gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 383
 384          /*
 385          * Set all global interrupts to this CPU only.
 386          */
 387          for (j = 0; j < gic_irqs; j += 4)
 388          {
 389                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET +  (j * 4) / 4);
 390                  dsb();
 391          }
 392          gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
 393
 394          //pri
 395          for (j = 0; j < gic_irqs; j += 4)
 396          {
 397                  writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 398
 399                  dsb();
 400          }
 401          gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 402
 403
 404          //secu
 405          for (j = 0; j < gic_irqs; j += 32)
 406          {
 407                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4 )/ 32);
 408                  dsb();
 409          }
 410          gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
 411
 412          //pending
 413          for (j = irqstart; j < gic_irqs; j += 32)
 414          {
 415                  //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
 416                  i++;
 417                  dsb();
 418          }
 419          gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 420
 421          //disable
 422 #if 0
 423          for (j = 0; j < gic_irqs; j += 32)
 424          {
 425                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 426                  dsb();
 427          }
 428          gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 429
 430 #else
 431         for (j = irqstart; j < gic_irqs; j += 32)
 432             writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 433         writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 434         writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 435 #endif
 436
 437          //enable
 438          for (j = 0; j < gic_irqs; j += 32)
 439          {
 440                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 441
 442                  dsb();
 443          }
 444
 445          gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 446
 447          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
 448          writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
 449          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
 450
 451          gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 452          gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 453
 454 }
 455
 456 /**************************************regs save and resume**************************/
 457
 458 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
 459 {
 460      u32 i;
 461          u32 cnt=(end_offset-st_offset)/4+1;
 462      for(i=0;i<cnt;i++)
 463      {
 464          data[i]=readl_relaxed(base+st_offset+i*4);
 465      }
 466 }
 467
 468 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
 469 {
 470      u32 i;
 471      u32 cnt=(end_offset-st_offset)/4+1;
 472      for(i=0;i<cnt;i++)
 473      {
 474          reg_writel(data[i]|w_msk,(base+st_offset+i*4));
 475      }
 476 }
 477
 478 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
 479 {
 480         u32 i;
 481         u32 cnt=(end_offset-st_offset)/4+1;
 482          for(i=0;i<cnt;i++)
 483          {
 484                  reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
 485          }
 486 }
 487
 488 /**************************************uarts save and resume**************************/
 489
 490 #define RK3288_UART_NUM (4)
 491
 492 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
 493 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
 494
 495 #define UART_DLL        0       /* Out: Divisor Latch Low */
 496 #define UART_DLM        1       /* Out: Divisor Latch High */
 497
 498 #define UART_IER        1
 499 #define UART_FCR        2
 500
 501 #define UART_LCR        3       /* Out: Line Control Register */
 502 #define UART_MCR        4
 503
 504 #if 0 //
 505 static u32 slp_uart_data[RK3288_UART_NUM][10];
 506 static u32 slp_uart_data_flag[RK3288_UART_NUM];
 507
 508  void slp_uart_save(int ch)
 509  {
 510          int i=0;
 511         void __iomem *b_addr=slp_uart_base[ch];
 512          int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 513          u32 gate_reg;
 514          if(b_addr==NULL || ch>=RK3288_UART_NUM)
 515                 return;
 516
 517         if(ch==2)
 518         {
 519             idx=RK3288_CLKGATE_PCLK_UART2;
 520             b_addr=RK_DEBUG_UART_VIRT;
 521         }
 522
 523
 524         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 525         RK3288_CRU_UNGATING_OPS(idx);
 526          i=0;
 527          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
 528          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 529
 530          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
 531          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
 532
 533          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 534          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
 535          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
 536          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
 537
 538         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 539
 540  }
 541
 542  void slp_uart_resume(int ch)
 543  {
 544         int i=0;
 545
 546         u32 temp;
 547         void __iomem *b_addr=slp_uart_base[ch];
 548         int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 549         u32 gate_reg;
 550
 551         //rkpm_ddr_printascii("\nch");
 552      //   rkpm_ddr_printhex(b_addr);
 553
 554         if(b_addr==NULL || ch>=RK3288_UART_NUM)
 555             return;
 556
 557         if(ch==2)
 558             idx=RK3288_CLKGATE_PCLK_UART2;
 559
 560         //rkpm_ddr_printhex(ch);
 561
 562         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 563         RK3288_CRU_UNGATING_OPS(idx);
 564
 565          i=0;
 566          temp=slp_uart_data[ch][i++];
 567          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 568
 569          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
 570          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
 571
 572          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 573
 574          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
 575          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
 576          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
 577
 578          writel_relaxed(temp,b_addr+UART_LCR*4);
 579
 580          cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 581  }
 582 #endif
 583  void slp_uartdbg_resume(void)
 584 {
 585     void __iomem *b_addr=RK_DEBUG_UART_VIRT;
 586     u32 pclk_id=RK3288_CLKGATE_PCLK_UART2,clk_id=(RK3288_CLKGATE_UART0_SRC+2*2);
 587     u32 gate_reg[2];
 588     u32 rfl_reg,lsr_reg;
 589
 590     gate_reg[0]=cru_readl(RK3288_CRU_GATEID_CONS(pclk_id));
 591     gate_reg[1]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id));
 592
 593     RK3288_CRU_UNGATING_OPS(pclk_id);
 594     // 24M is no gating setting
 595     ddr_pin_set_fun(0x7,0xc,0x6,0x0);
 596     ddr_pin_set_fun(0x7,0xc,0x7,0x0);
 597
 598     do{
 599             // out clk sel 24M
 600             cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 601
 602             //uart2 dbg reset
 603             cru_writel(0|CRU_W_MSK_SETBITS(1,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 604             dsb();
 605             dsb();
 606             rkpm_udelay(10);
 607             cru_writel(0|CRU_W_MSK_SETBITS(0,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 608
 609         #if 0
 610             //out clk (form pll)  is gating
 611             RK3288_CRU_GATING_OPS(clk_id);
 612             //out clk form pll gating to disable uart clk out
 613             // div 12
 614             cru_writel(CRU_W_MSK_SETBITS(11,0,0x7f), RK3288_CRU_CLKSELS_CON(15));
 615             dsb();
 616             dsb();
 617             dsb();
 618             dsb();
 619             cru_writel(CRU_W_MSK_SETBITS(0,8,0x3) , RK3288_CRU_CLKSELS_CON(15));
 620          #endif
 621
 622
 623             reg_writel(0x83,b_addr+UART_LCR*4);
 624
 625             reg_writel(0xd,b_addr+UART_DLL*4);
 626             reg_writel(0x0,b_addr+UART_DLM*4);
 627
 628             reg_writel(0x3,b_addr+UART_LCR*4);
 629
 630             reg_writel(0x5,b_addr+UART_IER*4);
 631             reg_writel(0xc1,b_addr+UART_FCR*4);
 632
 633             rfl_reg=readl_relaxed(b_addr+0x84);
 634             lsr_reg=readl_relaxed(b_addr+0x14);
 635
 636         }while((rfl_reg&0x1f)||(lsr_reg&0xf));
 637
 638         // out clk sel 24M
 639         cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 640
 641         ddr_pin_set_fun(0x7,0xc,0x6,0x1);
 642         ddr_pin_set_fun(0x7,0xc,0x7,0x1);
 643         cru_writel(gate_reg[0]|CRU_W_MSK(pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(pclk_id));
 644         cru_writel(gate_reg[1]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
 645 }
 646
 647 /**************************************i2c save and resume**************************/
 648
 649 //#define RK3288_I2C_REG_DUMP
 650 #define RK3288_I2C_NUM (6)
 651 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
 652 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
 653
 654 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
 655
 656 void slp_i2c_save(int ch)
 657 {
 658
 659         void __iomem *b_addr=slp_i2c_base[ch];
 660         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 661         u32 gate_reg;
 662
 663         if(!b_addr)
 664                 return;
 665
 666         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 667         RK3288_CRU_UNGATING_OPS(idx);
 668
 669         #ifdef RK3288_I2C_REG_DUMP
 670         rkpm_ddr_printascii("i2c save");
 671         rkpm_ddr_printhex(ch);
 672         rkpm_ddr_printch('\n');
 673         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 674         #endif
 675
 676         slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
 677
 678
 679         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 680
 681 }
 682 void slp_i2c_resume(int ch)
 683 {
 684         void __iomem *b_addr=slp_i2c_base[ch];
 685         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 686         u32 gate_reg;
 687
 688         if(!b_addr)
 689                 return;
 690         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 691         RK3288_CRU_UNGATING_OPS(idx);
 692
 693         slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
 694
 695         #ifdef RK3288_I2C_REG_DUMP
 696         rkpm_ddr_printascii("i2c resume");
 697         rkpm_ddr_printhex(ch);
 698         rkpm_ddr_printch('\n');
 699         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 700         #endif
 701
 702         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 703 }
 704
 705 /**************************************gpios save and resume**************************/
 706 #define RK3288_GPIO_CH (9)
 707 #if 0 //fun is ok ,not used
 708
 709 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
 710 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
 711 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
 712 static void gpio_ddr_dump_reg(int ports)
 713 {
 714     void __iomem *b_addr=RK_GPIO_VIRT(ports);
 715
 716     rkpm_ddr_printascii("gpio-");
 717     rkpm_ddr_printhex(ports);
 718     rkpm_ddr_printhex('\n');
 719
 720     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
 721     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
 722     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
 723     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
 724     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
 725     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
 726     rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
 727     rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
 728     rkpm_ddr_printhex('\n');
 729
 730     rkpm_ddr_printascii("iomux\n");
 731     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 732
 733     rkpm_ddr_printascii("iomux\n");
 734     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 735
 736 }
 737  static void slp_pin_gpio_save(int ports)
 738  {
 739         int i;
 740         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 741         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 742         u32 gate_reg;
 743
 744         if(ports==0||ports>=RK3288_GPIO_CH)
 745                 return;
 746
 747          gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 748          RK3288_CRU_UNGATING_OPS(idx);
 749
 750          //gpio_ddr_dump_reg(ports);
 751          i=0;
 752          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
 753          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
 754          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
 755          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
 756          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
 757          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
 758          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
 759          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
 760
 761         if(ports>0)
 762         {
 763             slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 764             slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 765          }
 766
 767
 768         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 769
 770  }
 771
 772  static void slp_pin_gpio_resume (int ports)
 773  {
 774          int i;
 775         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 776         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 777          u32 gate_reg;
 778
 779          if(ports==0||ports>=RK3288_GPIO_CH)
 780                 return;
 781           gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 782          RK3288_CRU_UNGATING_OPS(idx);
 783
 784
 785         if(ports>0)
 786         {
 787             slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
 788             slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
 789         }
 790
 791         i=0;
 792         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
 793         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
 794         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
 795         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
 796         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
 797         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
 798         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
 799         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
 800
 801         //gpio_ddr_dump_reg(ports);
 802         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 803
 804  }
 805
 806 #endif
 807  static inline u32 rkpm_l2_config(void)
 808  {
 809      u32 l2ctlr;
 810      asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
 811       return l2ctlr;
 812  }
 813
 814 static inline u32 rkpm_armerrata_818325(void)
 815 {
 816     u32 armerrata;
 817     asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (armerrata));
 818     return armerrata;
 819 }
 820
 821
 822
 823 /**************************************sleep func**************************/
 824
 825 void ddr_reg_save(uint32_t *pArg);
 826 void fiq_glue_resume(void);
 827 void rk30_cpu_resume(void);
 828 void rk30_l2_cache_init_pm(void);
 829 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
 830 void ddr_cfg_to_lp_mode(void);
 831 void l2x0_inv_all_pm(void);
 832 void rk30_cpu_while_tst(void);
 833
 834 #if 0
 835 static u32 slp_grf_soc_con_data[5];
 836 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
 837
 838 static u32 slp_grf_cpu_con_data[5];
 839 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
 840
 841 static u32 slp_grf_uoc0_con_data[4];
 842 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
 843
 844 static u32 slp_grf_uoc1_con_data[2];
 845 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
 846
 847 static u32 slp_grf_uoc2_con_data[2];
 848 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
 849
 850 static u32 slp_grf_uoc3_con_data[2];
 851 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
 852
 853 #endif
 854 //static u32 slp_pmu_pwrmode_con_data[1];
 855
 856
 857 //static u32 slp_nandc_data[8];
 858 //static void __iomem *rk30_nandc_base=NULL;
 859
 860 #define MS_37K (37)
 861 #define US_24M (24)
 862
 863 void inline pm_io_base_map(void)
 864 {
 865         int i;
 866         for(i=0;i<RK3288_I2C_NUM;i++)
 867             slp_i2c_base[i]  = ioremap(slp_i2c_phy[i], 0x1000);
 868
 869         for(i=0;i<RK3288_UART_NUM;i++)
 870             {
 871                 if(i!=CONFIG_RK_DEBUG_UART)
 872                     slp_uart_base[i]  = ioremap(slp_uart_phy[i], 0x1000);
 873                 else
 874                     slp_uart_base[i] = RK_DEBUG_UART_VIRT;
 875             }
 876
 877 }
 878 enum rk3288_pwr_mode_con {
 879
 880         pmu_pwr_mode_en=0,
 881         pmu_clk_core_src_gate_en,
 882         pmu_global_int_disable,
 883         pmu_l2flush_en,
 884
 885         pmu_bus_pd_en,
 886         pmu_a12_0_pd_en,
 887         pmu_scu_en,
 888         pmu_pll_pd_en,
 889
 890         pmu_chip_pd_en, // power off pin enable
 891         pmu_pwroff_comb,
 892         pmu_alive_use_lf,
 893         pmu_pmu_use_lf,
 894
 895         pmu_osc_24m_dis,
 896         pmu_input_clamp_en,
 897         pmu_wakeup_reset_en,
 898         pmu_sref0_enter_en,
 899
 900         pmu_sref1_enter_en,
 901         pmu_ddr0io_ret_en,
 902         pmu_ddr1io_ret_en,
 903         pmu_ddr0_gating_en,
 904
 905         pmu_ddr1_gating_en,
 906         pmu_ddr0io_ret_de_req,
 907         pmu_ddr1io_ret_de_req
 908
 909 };
 910  enum rk3288_pwr_mode_con1 {
 911
 912         pmu_clr_bus=0,
 913         pmu_clr_core,
 914         pmu_clr_cpup,
 915         pmu_clr_alive,
 916
 917         pmu_clr_dma,
 918         pmu_clr_peri,
 919         pmu_clr_gpu,
 920         pmu_clr_video,
 921         pmu_clr_hevc,
 922         pmu_clr_vio
 923
 924 };
 925  static u32 rk3288_powermode=0;
 926 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
 927
 928 static u32 sgrf_soc_con0,pmu_wakeup_cfg0,pmu_wakeup_cfg1,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
 929
 930 static u32  rkpm_slp_mode_set(u32 ctrbits)
 931 {
 932     u32 mode_set,mode_set1;
 933     // setting gpio0_a0 arm off pin
 934
 935     sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 936
 937     pmu_wakeup_cfg0=pmu_readl(RK3288_PMU_WAKEUP_CFG0);
 938     pmu_wakeup_cfg1=pmu_readl(RK3288_PMU_WAKEUP_CFG1);
 939
 940     pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
 941     pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
 942
 943     ddr_pin_set_fun(0x0,0xa,0x0,0x1);
 944
 945
 946
 947     //mode_set1=pmu_pwr_mode_con1;
 948     //mode_set=pmu_pwr_mode_con0;
 949
 950    //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 951    pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
 952
 953     // enable boot ram
 954     reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 955     dsb();
 956
 957     reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
 958     dsb();
 959
 960     mode_set=  BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
 961      mode_set1=0;
 962
 963     if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
 964     {
 965         rkpm_ddr_printascii("-autoidle-");
 966         mode_set|=BIT(pmu_clk_core_src_gate_en);
 967     }
 968     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
 969     {
 970         rkpm_ddr_printascii("-armdp-");
 971         mode_set |= BIT(pmu_a12_0_pd_en)
 972                         | BIT(pmu_sref0_enter_en) | BIT(pmu_sref1_enter_en)
 973                         | BIT(pmu_ddr0_gating_en) | BIT(pmu_ddr1_gating_en)
 974                         | BIT(pmu_chip_pd_en);
 975     }
 976     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
 977     {
 978         rkpm_ddr_printascii("-armoff-");
 979         mode_set|=BIT(pmu_scu_en)
 980                             //|BIT(pmu_a12_0_pd_en)
 981                             |BIT(pmu_clk_core_src_gate_en) // »½ÐÑºóÒì³£
 982                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 983                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 984                             //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 985                             |BIT(pmu_chip_pd_en);
 986         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 987                                 |BIT(pmu_clr_alive)
 988                                 |BIT(pmu_clr_peri)
 989                                 |BIT(pmu_clr_bus)
 990                                 |BIT(pmu_clr_dma)
 991                                 ;
 992     }
 993     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
 994     {
 995
 996         rkpm_ddr_printascii("-armoff-logdp-");
 997
 998         mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
 999                             |BIT(pmu_chip_pd_en)
1000                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
1001                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
1002                             |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
1003                             |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
1004                             ;
1005         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
1006                            |BIT(pmu_clr_alive)
1007                            |BIT(pmu_clr_peri)
1008                            |BIT(pmu_clr_bus)
1009                            |BIT(pmu_clr_dma)
1010                           ;
1011
1012     }
1013     else
1014     {
1015         mode_set=0;
1016         mode_set1=0;
1017     }
1018
1019
1020     if(mode_set&BIT(pmu_osc_24m_dis))
1021     {
1022         rkpm_ddr_printascii("osc_off");
1023         pmu_writel(32*30,RK3288_PMU_OSC_CNT);
1024         pmu_writel(32*30,RK3288_PMU_STABL_CNT);
1025     } else if (mode_set & BIT(pmu_a12_0_pd_en)) {
1026         pmu_writel(0x0, RK3288_PMU_STABL_CNT);
1027         pmu_writel(0x0, RK3288_PMU_OSC_CNT);
1028         pmu_writel(0x0, RK3288_PMU_PLL_CNT);
1029         pmu_writel(0x0, RK3288_PMU_DDR0IO_PWRON_CNT);
1030         pmu_writel(0x0, RK3288_PMU_DDR1IO_PWRON_CNT);
1031         pmu_writel(0x0, RK3288_PMU_GPU_PWRUP_CNT);
1032         pmu_writel(0x0, RK3288_PMU_WAKEUP_RST_CLR_CNT);
1033         /*pmu_writel(100,RK3288_PMU_CORE_PWRUP_CNT);*/
1034         } else
1035         pmu_writel(24*1000*10, RK3288_PMU_STABL_CNT);
1036
1037     if(mode_set&BIT(pmu_ddr0io_ret_en))
1038     {
1039         rkpm_ddr_printascii("ddrc_off");
1040         ddr_pin_set_fun(0x0,0xa,0x1,0x1);
1041         ddr_pin_set_fun(0x0,0xa,0x2,0x1);
1042         ddr_pin_set_fun(0x0,0xa,0x3,0x1);
1043     }
1044
1045     pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
1046     pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
1047
1048   //  rkpm_ddr_printhex(mode_set);
1049   //  rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1050
1051     return (pmu_readl(RK3288_PMU_PWRMODE_CON));
1052 }
1053
1054 static inline void  rkpm_slp_mode_set_resume(void)
1055 {
1056
1057     pmu_writel(pmu_wakeup_cfg0,RK3288_PMU_WAKEUP_CFG0);
1058     pmu_writel(pmu_wakeup_cfg1,RK3288_PMU_WAKEUP_CFG1);
1059
1060     pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
1061     pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
1062     reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
1063
1064 }
1065
1066 static void sram_code_data_save(u32 pwrmode)
1067 {
1068         char *code_src,*data_src;
1069         u32 code_size,data_size;
1070
1071
1072         //u32 *p;
1073         if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1074         {
1075             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1076             sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1077
1078             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=1;
1079             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325]=rkpm_armerrata_818325();//
1080
1081             sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1082             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1083             #if 0
1084             rkpm_ddr_printascii("l2&arm_errata--");
1085             rkpm_ddr_printhex(rkpm_l2_config());
1086             rkpm_ddr_printhex(rkpm_armerrata_818325());
1087             rkpm_ddr_printascii("\n");
1088             #endif
1089         }
1090         else
1091         {
1092             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=0;
1093             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=0;
1094             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1095             return ;
1096         }
1097
1098         if(pwrmode&BIT(pmu_bus_pd_en))
1099         {
1100                 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1101                 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1102                 code_src=(char *)ddr_get_resume_code_info(&code_size);
1103                 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1104                 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1105                 data_src=(char *)ddr_get_resume_data_info(&data_size);
1106                 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1107        }
1108         else
1109         {
1110             sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1111         }
1112
1113         sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1114
1115         flush_cache_all();
1116         outer_flush_all();
1117         local_flush_tlb_all();
1118
1119 }
1120
1121 static inline void sram_code_data_resume(u32 pwrmode)
1122 {
1123          if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1124         {
1125              sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1126         }
1127
1128 }
1129
1130 static void  rkpm_peri_save(u32 power_mode)
1131 {
1132 //    u32 gpio_gate[2];
1133
1134         if (power_mode & (BIT(pmu_scu_en) | BIT(pmu_a12_0_pd_en)))
1135                 rkpm_gic_dist_save(&slp_gic_save[0]);
1136 #if 0
1137     gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1138     gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1139     RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1140     cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1141                          RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1142 #endif
1143
1144     if(power_mode&BIT(pmu_bus_pd_en))
1145    {
1146        #if 0
1147         //gpio7_c6
1148         //gpio7_c7
1149         ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1150         ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1151         ddr_pin_set_fun(7,0xc,0x6,0);
1152
1153         ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1154         ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1155         ddr_pin_set_fun(7,0xc,0x7,0);
1156         #endif
1157         //slp_uart_save(2);
1158         #if 0
1159         ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1160         ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1161         ddr_pin_set_fun(0,0xb,0x7,0);
1162
1163         ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1164         ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1165         ddr_pin_set_fun(0,0xc,0x0,0);
1166         #endif
1167         slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1168         slp_i2c_save(1);//i2c audio
1169     }
1170
1171 #if 0
1172         cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1173                                       RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1174         cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1175 #endif
1176
1177 }
1178
1179 static inline void  rkpm_peri_resume(u32 power_mode)
1180 {
1181         if (power_mode & (BIT(pmu_scu_en) | BIT(pmu_a12_0_pd_en))) {
1182                 /*fiq_glue_resume();*/
1183                 rkpm_gic_dist_resume(&slp_gic_save[0]);
1184                 fiq_glue_resume();
1185                 /*rkpm_ddr_printascii("gic res");*/
1186         }
1187     if(power_mode&BIT(pmu_bus_pd_en))
1188    {
1189         slp_i2c_resume(0);// i2c pmu
1190         slp_i2c_resume(1);//i2c audio
1191     }
1192
1193 }
1194
1195 static u32 pdbus_gate_reg[5];
1196 static inline void  rkpm_peri_resume_first(u32 power_mode)
1197 {
1198
1199     if(power_mode&BIT(pmu_bus_pd_en))
1200     {
1201         cru_writel(0xffff0000|pdbus_gate_reg[0],RK3288_CRU_CLKGATES_CON(0));
1202         cru_writel(0xffff0000|pdbus_gate_reg[1],RK3288_CRU_CLKGATES_CON(4));
1203         cru_writel(0xffff0000|pdbus_gate_reg[2],RK3288_CRU_CLKGATES_CON(5));
1204         cru_writel(0xffff0000|pdbus_gate_reg[3],RK3288_CRU_CLKGATES_CON(10));
1205         cru_writel(0xffff0000|pdbus_gate_reg[4],RK3288_CRU_CLKGATES_CON(11));
1206     }
1207
1208
1209       if(power_mode&BIT(pmu_bus_pd_en))
1210         slp_uartdbg_resume();
1211 }
1212
1213 static void rkpm_slp_setting(void)
1214 {
1215     rk_usb_power_down();
1216
1217     if(rk3288_powermode&BIT(pmu_bus_pd_en))
1218     {
1219         // pd bus will be power down ,but if it reup,ungating clk for its reset
1220         // ungating pdbus clk
1221         pdbus_gate_reg[0]=cru_readl(RK3288_CRU_CLKGATES_CON(0));
1222         pdbus_gate_reg[1]=cru_readl(RK3288_CRU_CLKGATES_CON(4));
1223         pdbus_gate_reg[2]=cru_readl(RK3288_CRU_CLKGATES_CON(5));
1224         pdbus_gate_reg[3]=cru_readl(RK3288_CRU_CLKGATES_CON(10));
1225         pdbus_gate_reg[4]=cru_readl(RK3288_CRU_CLKGATES_CON(11));
1226
1227         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(0));
1228         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(4));
1229         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(5));
1230         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(10));
1231         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(11));
1232
1233         RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_UART2);
1234        // RK3288_CRU_UNGATING_OPS((RK3288_CLKGATE_UART0_SRC+2*2));
1235        //c2c host
1236        RK3288_CRU_UNGATING_OPS(RK3288_CRU_CONS_GATEID(13)+8);
1237
1238     }
1239
1240 }
1241
1242
1243 static void rkpm_save_setting_resume_first(void)
1244 {
1245         rk_usb_power_up();
1246         rkpm_peri_resume_first(rk3288_powermode);
1247
1248         // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1249         #if 0
1250         //rk319x_pm_set_power_domain(PD_PERI,true);
1251         //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1252         slp_pin_gpio_resume(1);
1253         slp_pin_gpio_resume(2);
1254         slp_pin_gpio_resume(3);
1255         slp_pin_gpio_resume(4);
1256
1257         #if 0
1258         slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1259         slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1260
1261         slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1262         slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1263         slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1264         slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1265         #endif
1266         //sram_printch_uart_enable();
1267         slp_uart_resume(2);
1268        #endif
1269 }
1270
1271 static void rkpm_save_setting(u32 ctrbits)
1272 {
1273
1274 #if 0
1275     rkpm_ddr_regs_dump(RK_DDR_VIRT,0,0x3fc);
1276     rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE,0,0x294);
1277
1278     rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE+RK3288_DDR_PUBL_SIZE,0,0x3fc);
1279     rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE*2+RK3288_DDR_PUBL_SIZE,0,0x294);
1280 #endif
1281     rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1282     if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1283     {
1284             sram_code_data_save(rk3288_powermode);
1285             rkpm_peri_save(rk3288_powermode);
1286     }
1287     else
1288          return ;
1289
1290 }
1291 static void rkpm_save_setting_resume(void)
1292 {
1293
1294         #if 0
1295         rkpm_ddr_printascii("l2&arm_errata--");
1296         rkpm_ddr_printhex(rkpm_l2_config());
1297         rkpm_ddr_printhex(rkpm_armerrata_818325());
1298         rkpm_ddr_printascii("\n");
1299         #endif
1300
1301          if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1302         {
1303             sram_code_data_resume(rk3288_powermode);
1304             rkpm_peri_resume(rk3288_powermode);
1305         }
1306          rkpm_slp_mode_set_resume();
1307
1308 }
1309
1310 /*******************************common code  for rkxxx*********************************/
1311 static void  inline uart_printch(char byte)
1312 {
1313         u32 reg_save[2];
1314         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART*2);
1315         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1316
1317         if(CONFIG_RK_DEBUG_UART==4)
1318             u_clk_id=RK3288_CLKGATE_UART4_SRC;
1319         if(CONFIG_RK_DEBUG_UART==2)
1320             u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1321
1322         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1323         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1324         RK3288_CRU_UNGATING_OPS(u_clk_id);
1325         RK3288_CRU_UNGATING_OPS(u_pclk_id);
1326
1327         rkpm_udelay(1);
1328
1329 write_uart:
1330         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1331         dsb();
1332
1333         /* loop check LSR[6], Transmitter Empty bit */
1334         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1335                 barrier();
1336
1337         if (byte == '\n') {
1338                 byte = '\r';
1339                 goto write_uart;
1340         }
1341
1342          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1343          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1344 }
1345
1346 void PIE_FUNC(sram_printch)(char byte)
1347 {
1348         uart_printch(byte);
1349 }
1350
1351 static void pll_udelay(u32 udelay);
1352
1353 #ifdef CONFIG_RK_LAST_LOG
1354 extern void rk_last_log_text(char *text, size_t size);
1355 #endif
1356
1357 static void  ddr_printch(char byte)
1358 {
1359         uart_printch(byte);
1360
1361 #ifdef CONFIG_RK_LAST_LOG
1362         rk_last_log_text(&byte, 1);
1363
1364         if (byte == '\n') {
1365                 byte = '\r';
1366                 rk_last_log_text(&byte, 1);
1367         }
1368 #endif
1369         pll_udelay(2);
1370 }
1371 /*******************************gpio func*******************************************/
1372 //#define RK3288_PMU_GPIO0_A_IOMUX      0x0084
1373 //#define RK3288_PMU_GPIO0_B_IOMUX      0x0088
1374 //#define RK3288_PMU_GPIO0_C_IOMUX      0x008c
1375 //#define RK3288_PMU_GPIO0_D_IOMUX      0x0090
1376 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1377 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1378 {
1379         u32 off_set;
1380         bank-=0xa;
1381
1382         if(port==0)
1383         {
1384             if(bank>2)
1385                 return;
1386             off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1387             pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1388         }
1389         else if(port==1||port==2)
1390         {
1391             off_set=port*(4*4)+bank*4;
1392             reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1393         }
1394         else if(port==3)
1395         {
1396             if(bank<=2)
1397             {
1398                 off_set=0x20+bank*4;
1399                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1400
1401             }
1402             else
1403             {
1404                 off_set=0x2c+(b_gpio/4)*4;
1405                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1406             }
1407
1408         }
1409         else if(port==4)
1410         {
1411             if(bank<=1)
1412             {
1413                 off_set=0x34+bank*8+(b_gpio/4)*4;
1414                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1415             }
1416             else
1417             {
1418                 off_set=0x44+(bank-2)*4;
1419                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1420             }
1421
1422         }
1423         else if(port==5||port==6)
1424         {
1425                 off_set=0x4c+(port-5)*4*4+bank*4;
1426                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1427         }
1428         else if(port==7)
1429         {
1430             if(bank<=1)
1431             {
1432                 off_set=0x6c+bank*4;
1433                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1434             }
1435             else
1436             {
1437                 off_set=0x74+(bank-2)*8+(b_gpio/4)*4;
1438                 //rkpm_ddr_printascii("gpio");
1439                 //rkpm_ddr_printhex(off_set);
1440                 //rkpm_ddr_printascii("-");
1441                 //rkpm_ddr_printhex((b_gpio%4)*4);
1442
1443                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1444
1445                 //rkpm_ddr_printhex(reg_readl(RK_GRF_VIRT+0+off_set));
1446                 //rkpm_ddr_printascii("\n");
1447             }
1448
1449         }
1450         else if(port==8)
1451         {
1452             if(bank<=1)
1453             {
1454                 off_set=0x80+bank*4;
1455                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1456             }
1457         }
1458
1459 }
1460
1461 #if 0
1462 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1463 {
1464
1465 }
1466 #endif
1467 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1468 {
1469     u32 off_set;
1470
1471     bank-=0xa;
1472
1473     if(port > 0)
1474     {
1475         //gpio1_d st
1476         //if(port==1&&bank<3)
1477        //  return;
1478         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1479         off_set=(0x14c-0x1c)+port*(4*4)+bank*4;
1480
1481         #if 0
1482         rkpm_ddr_printascii("gpio pull\n");
1483         rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1484         rkpm_ddr_printhex(b_gpio);
1485         rkpm_ddr_printhex(pull);
1486         rkpm_ddr_printhex(off_set);
1487         rkpm_ddr_printhex(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3));
1488         #endif
1489
1490         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1491
1492     }
1493     else
1494     {
1495         if(bank>2)// gpio0_d is not support
1496             return;
1497         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1498     }
1499
1500 }
1501
1502 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1503 {
1504     u32 off_set;
1505
1506     bank-=0xa;
1507
1508     if(port > 0)
1509     {
1510         //gpio1_d st
1511         if(port==1&&bank<3)
1512             return 0;
1513         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1514         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1515         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1516
1517     }
1518     else
1519     {
1520         if(bank>2)// gpio0_d is not support
1521             return 0;
1522         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1523     }
1524
1525 }
1526
1527
1528 //RKPM_GPIOS_INPUT
1529 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1530 {
1531     u32 val;
1532
1533     bank-=0xa;
1534     b_gpio=bank*8+b_gpio;//
1535
1536     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1537
1538     if(type==RKPM_GPIO_OUTPUT)
1539         val|=(0x1<<b_gpio);
1540     else
1541         val&=~(0x1<<b_gpio);
1542     #if 0
1543     rkpm_ddr_printascii("gpio out\n");
1544     rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1545     rkpm_ddr_printhex(b_gpio);
1546
1547     rkpm_ddr_printhex(type);
1548     rkpm_ddr_printhex(val);
1549     #endif
1550     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1551
1552     //rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR));
1553
1554
1555 }
1556
1557 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1558 {
1559     bank-=0xa;
1560     b_gpio=bank*8+b_gpio;
1561     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1562 }
1563
1564 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
1565 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1566 {
1567     u32 val;
1568
1569     bank-=0xa;
1570     b_gpio=bank*8+b_gpio;
1571
1572     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1573
1574     if(level==RKPM_GPIO_OUT_H)
1575         val|=(0x1<<b_gpio);
1576     else //
1577         val&=~(0x1<<b_gpio);
1578
1579      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1580 }
1581
1582 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1583 {
1584     bank-=0xa;
1585     b_gpio=bank*8+b_gpio;
1586     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1587 }
1588
1589 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1590 {
1591
1592     bank-=0xa;
1593     b_gpio=bank*8+b_gpio;
1594
1595     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1596 }
1597 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1598 {
1599     u32 val;
1600
1601     bank-=0xa;
1602     b_gpio=bank*8+b_gpio;
1603
1604     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1605     rkpm_ddr_printascii("\n inten:");
1606     rkpm_ddr_printhex(val);
1607
1608     rkpm_ddr_printascii("-");
1609     if(en==1)
1610         val|=(0x1<<b_gpio);
1611     else //
1612         val&=~(0x1<<b_gpio);
1613
1614     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1615     dsb();
1616
1617      rkpm_ddr_printhex(val);
1618      rkpm_ddr_printascii("-");
1619
1620      rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1621
1622     rkpm_ddr_printascii("\n");
1623
1624
1625 }
1626 #if 0
1627 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1628 {
1629         pin_set_fun(port,bank,b_gpio,fun);
1630 }
1631 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1632 {
1633     return pin_get_funset(port,bank,b_gpio);
1634 }
1635
1636 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1637 {
1638         pin_set_pull(port,bank,b_gpio,fun);
1639 }
1640 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1641 {
1642     return pin_get_pullset(port,bank,b_gpio);
1643 }
1644
1645 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1646 {
1647     gpio_set_in_output(port,bank,b_gpio,type);
1648 }
1649
1650 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1651 {
1652     return gpio_get_in_outputset(port,bank,b_gpio);
1653 }
1654
1655 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1656 {
1657
1658     gpio_set_output_level(port,bank,b_gpio,level);
1659
1660 }
1661
1662 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1663 {
1664     return gpio_get_output_levelset(port,bank,b_gpio);
1665 }
1666 #endif
1667 #if 0
1668 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1669 {
1670     return gpio_get_input_level(port,bank,b_gpio);
1671 }
1672 #endif
1673 //ddr
1674 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1675 {
1676         pin_set_fun(port,bank,b_gpio,fun);
1677 }
1678 #if 0
1679 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1680 {
1681     return pin_get_funset(port,bank,b_gpio);
1682 }
1683 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1684 {
1685     return pin_get_pullset(port,bank,b_gpio);
1686 }
1687 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1688 {
1689     return gpio_get_in_outputset(port,bank,b_gpio);
1690 }
1691
1692 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1693 {
1694     return gpio_get_output_levelset(port,bank,b_gpio);
1695 }
1696 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1697 {
1698     return gpio_get_input_level(port,bank,b_gpio);
1699 }
1700
1701
1702 #endif
1703
1704
1705 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1706 {
1707         pin_set_pull(port,bank,b_gpio,fun);
1708 }
1709
1710 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1711 {
1712     gpio_set_in_output(port,bank,b_gpio,type);
1713 }
1714 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1715 {
1716     gpio_set_output_level(port,bank,b_gpio,level);
1717 }
1718
1719
1720
1721 #define GPIO_DTS_NUM (20)
1722 static  u32 suspend_gpios[GPIO_DTS_NUM];
1723 static  u32 resume_gpios[GPIO_DTS_NUM];
1724
1725 static int of_find_property_value_getsize(const struct device_node *np,const char *propname)
1726 {
1727         struct property *prop = of_find_property(np, propname, NULL);
1728
1729         if (!prop)
1730                 return 0;
1731         if (!prop->value)
1732                 return 0;
1733         return prop->length;
1734 }
1735
1736 static  void rkpm_pin_gpio_config(u32 pin_gpio_bits)
1737 {
1738
1739     u32 pins;
1740     u8 port,bank,b_gpio,fun,in_out, level, pull;
1741
1742     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1743     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1744     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1745     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1746
1747     port=RKPM_PINBITS_PORT(pins);
1748     bank=RKPM_PINBITS_BANK(pins);
1749     b_gpio=RKPM_PINBITS_BGPIO(pins);
1750     fun=RKPM_PINBITS_FUN(pins);
1751
1752
1753     if(!fun)
1754    {
1755         if(in_out==RKPM_GPIO_OUTPUT)
1756         {
1757             if(level==RKPM_GPIO_OUT_L)
1758                 pull=RKPM_GPIO_PULL_DN;
1759             else
1760                 pull=RKPM_GPIO_PULL_UP;
1761
1762             ddr_gpio_set_output_level(port,bank,b_gpio,level);
1763         }
1764         //rkpm_ddr_printhex(pins);
1765
1766         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1767     }
1768
1769     ddr_pin_set_pull(port,bank,b_gpio,pull);
1770     ddr_pin_set_fun(port,bank,b_gpio,fun);
1771
1772
1773
1774 }
1775
1776 #define RKPM_PINGPIO_BITS_PINTOPORT(pin_gpio_bits) RKPM_PINBITS_PORT(RKPM_PINGPIO_BITS_PIN((pin_gpio_bits)))
1777 #define  rkpm_gpio_pclk_idx(port) ((port)==0) ? RK3288_CLKGATE_PCLK_GPIO0 : (RK3288_CLKGATE_PCLK_GPIO1+(port)-1)
1778
1779 //rk3288_powermode
1780 static void rkpm_pins_setting(u32 *gpios,u32 cnt)
1781 {
1782        u32 i,clk_id;
1783        u32 gpio_clk_reg[9];
1784        u8 port;
1785
1786       // rkpm_ddr_printascii("\ngpios");
1787
1788         for(i=0;i<9;i++)
1789         {
1790             gpio_clk_reg[i]=0xffff0000;
1791         }
1792
1793        for(i=0;i<cnt;i++)
1794        {
1795             if(gpios[i]!=0)
1796            {
1797                 port=RKPM_PINGPIO_BITS_PINTOPORT(gpios[i]);
1798                 if(gpio_clk_reg[port]==0xffff0000)
1799                 {
1800                     clk_id=rkpm_gpio_pclk_idx(port);
1801                     gpio_clk_reg[port]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id))&0xffff;
1802                     RK3288_CRU_UNGATING_OPS(clk_id);
1803                 }
1804                // rkpm_ddr_printhex(gpios[i]);
1805                 rkpm_pin_gpio_config(gpios[i]);
1806            }
1807        }
1808       // rkpm_ddr_printascii("\n");
1809
1810  #if 0
1811         for(i=0;i<9;i++)
1812        {
1813            rkpm_ddr_regs_dump(RK_GPIO_VIRT(i),0,0x4);
1814        }
1815        //
1816        rkpm_ddr_regs_dump(RK_GRF_VIRT,0xc,0x84);
1817        rkpm_ddr_regs_dump(RK_GRF_VIRT,0x14c,0x1b4);
1818      //  rkpm_ddr_regs_dump(RK_PMU_VIRT,0x64,0x6c);
1819        //rkpm_ddr_regs_dump(RK_PMU_VIRT,0x84,0x9c);
1820    #endif
1821
1822         for(i=0;i<9;i++)
1823        {
1824             if(gpio_clk_reg[i]!=0xffff0000)
1825             {
1826                 clk_id=rkpm_gpio_pclk_idx(i);
1827                 cru_writel(gpio_clk_reg[i]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
1828             }
1829        }
1830
1831 }
1832
1833 static void  rkpm_gpio_suspend(void)
1834 {
1835     rkpm_pins_setting(&suspend_gpios[0],GPIO_DTS_NUM);
1836 }
1837
1838
1839
1840 static void  rkpm_gpio_resume(void)
1841 {
1842      rkpm_pins_setting(&resume_gpios[0],GPIO_DTS_NUM);
1843 }
1844
1845 #if 1
1846 static void gpio_get_dts_info(struct device_node *parent)
1847 {
1848         int i;
1849         size_t temp_len;
1850     //return;
1851
1852         for(i=0;i<GPIO_DTS_NUM;i++)
1853         {
1854             suspend_gpios[i]=0;
1855             resume_gpios[i]=0;
1856         }
1857
1858      #if 1
1859         temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-suspend_gpios");
1860         if(temp_len)
1861         {
1862             printk("%s suspend:%d\n",__FUNCTION__,temp_len);
1863             if(temp_len)
1864             {
1865                 if(of_property_read_u32_array(parent,"rockchip,pmic-suspend_gpios",&suspend_gpios[0],temp_len/4))
1866                 {
1867                         suspend_gpios[0]=0;
1868                        printk("%s:get pm ctr error\n",__FUNCTION__);
1869                 }
1870             }
1871         }
1872
1873        temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-resume_gpios");
1874        if(temp_len)
1875        {
1876            printk("%s resume:%d\n",__FUNCTION__,temp_len);
1877            if(of_property_read_u32_array(parent,"rockchip,pmic-resume_gpios",&resume_gpios[0],temp_len/4))
1878            {
1879                     resume_gpios[0]=0;
1880                    printk("%s:get pm ctr error\n",__FUNCTION__);
1881            }
1882         }
1883      #endif
1884
1885      printk("rockchip,pmic-suspend_gpios:");
1886      for(i=0;i<GPIO_DTS_NUM;i++)
1887      {
1888          printk("%x ",suspend_gpios[i]);
1889          if(i==(GPIO_DTS_NUM-1))
1890              printk("\n");
1891      }
1892
1893      printk("rockchip,pmic-resume_gpios:");
1894      for(i=0;i<GPIO_DTS_NUM;i++)
1895      {
1896           printk("%x ",resume_gpios[i]);
1897           if(i==(GPIO_DTS_NUM-1))
1898               printk("\n");
1899      }
1900
1901    rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1902
1903 }
1904 #endif
1905
1906 /*******************************clk gating config*******************************************/
1907 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1908 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1909
1910
1911 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1912 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1913 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1914
1915
1916 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1917 static u32 *p_rkpm_clkgt_last_set;
1918
1919 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1920
1921 void PIE_FUNC(gtclks_sram_suspend)(void)
1922 {
1923     int i;
1924    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1925    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1926
1927     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1928     {
1929         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1930         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1931         #if 0
1932         rkpm_sram_printch('\n');
1933         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1934         rkpm_sram_printch('-');
1935         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1936         rkpm_sram_printch('-');
1937         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1938         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1939         rkpm_sram_printch('\n');
1940         #endif
1941     }
1942
1943         //RK3288_CRU_UNGATING_OPS(u_clk_id);
1944         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1945
1946 }
1947
1948 void PIE_FUNC(gtclks_sram_resume)(void)
1949 {
1950     int i;
1951     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1952     {
1953         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1954     }
1955 }
1956 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
1957 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
1958
1959 #define gpio7_readl(offset)     readl_relaxed(RK_GPIO_VIRT(7)+ offset)
1960 #define gpio7_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(7) + offset); dsb(); } while (0)
1961
1962 int gpio7_pin_data1, gpio7_pin_dir1;
1963 int gpio7_pin_iomux1;
1964
1965 static void gtclks_suspend(void)
1966 {
1967         int i;
1968
1969         gpio7_pin_data1= gpio7_readl(0);
1970         gpio7_pin_dir1 = gpio7_readl(0x04);
1971         gpio7_pin_iomux1 =  gpio7_readl(0x6c);
1972         grf_writel(0x00040000, 0x6c);
1973         gpio7_writel(gpio7_pin_dir1|0x2, 0x04);
1974         gpio7_writel((gpio7_pin_data1|2), 0x00);
1975
1976   // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1977                                           //          ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1978
1979     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1980     {
1981             clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1982            // 160 1a8
1983            #if 0
1984            if(
1985                // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1986                 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1987                 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1988               //  RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1989                 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1990                // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1991                // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
1992
1993
1994                 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
1995                // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
1996                // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
1997                // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
1998                 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
1999                 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
2000                 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
2001                 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
2002                 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
2003                 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
2004                 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
2005                // RK3288_CRU_CLKGATES_CON(i)==0x1a8
2006                RK3288_CRU_CLKGATES_CON(i)==0xfff
2007             )
2008             {
2009
2010                  cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
2011                // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2012
2013             }
2014            else
2015             #endif
2016             {
2017                // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
2018                CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2019            }
2020            #if 0
2021             rkpm_ddr_printch('\n');
2022             rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
2023             rkpm_ddr_printch('-');
2024             rkpm_ddr_printhex(clk_ungt_msk[i]);
2025             rkpm_ddr_printch('-');
2026             rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
2027             if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
2028             rkpm_ddr_printch('\n');
2029             #endif
2030     }
2031
2032 }
2033
2034 static void gtclks_resume(void)
2035 {
2036     int i;
2037      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2038     {
2039        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2040      }
2041      //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
2042                                                  //   ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
2043         grf_writel(0x00040004, 0x6c);
2044 }
2045 /********************************pll power down***************************************/
2046
2047 static void pm_pll_wait_lock(u32 pll_idx)
2048 {
2049         u32 delay = 600000U;
2050        // u32 mode;
2051      //  mode=cru_readl(RK3288_CRU_MODE_CON);
2052         dsb();
2053         dsb();
2054         dsb();
2055         dsb();
2056         dsb();
2057         dsb();
2058         while (delay > 0) {
2059                 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
2060                         break;
2061                 delay--;
2062         }
2063         if (delay == 0) {
2064                 rkpm_ddr_printascii("unlock-pll:");
2065                 rkpm_ddr_printhex(pll_idx);
2066                 rkpm_ddr_printch('\n');
2067         }
2068     //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
2069 }
2070
2071 static void pll_udelay(u32 udelay)
2072 {
2073     u32 mode;
2074     mode=cru_readl(RK3288_CRU_MODE_CON);
2075     // delay in 24m
2076     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2077
2078     rkpm_udelay(udelay*5);
2079
2080     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2081 }
2082
2083 static u32 plls_con0_save[END_PLL_ID];
2084 static u32 plls_con1_save[END_PLL_ID];
2085 static u32 plls_con2_save[END_PLL_ID];
2086 static u32 plls_con3_save[END_PLL_ID];
2087
2088 static u32 cru_mode_con;
2089
2090 static inline void plls_suspend(u32 pll_id)
2091 {
2092     plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
2093     plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
2094     plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
2095     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
2096
2097     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
2098
2099 }
2100 static inline void plls_resume_pre(u32 pll_id)
2101 {
2102         u32 pllcon0, pllcon1, pllcon2;
2103
2104         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
2105
2106         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id), 3));
2107         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id), 3));
2108
2109         pllcon0 = plls_con0_save[pll_id];
2110         pllcon1 = plls_con1_save[pll_id];
2111         pllcon2 = plls_con2_save[pll_id];
2112
2113         /*enter rest*/
2114         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id, 3));
2115         cru_writel(pllcon0 | CRU_W_MSK(0, 0xf) | CRU_W_MSK(8, 0x3f)
2116                 , RK3288_PLL_CONS(pll_id, 0));
2117         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id, 1));
2118         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id, 2));
2119 }
2120
2121 static inline void plls_resume(void)
2122 {
2123         plls_resume_pre(APLL_ID);
2124         plls_resume_pre(GPLL_ID);
2125         plls_resume_pre(CPLL_ID);
2126         plls_resume_pre(NPLL_ID);
2127
2128         pll_udelay(5);
2129
2130         /*return form rest*/
2131         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(APLL_ID, 3));
2132         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(GPLL_ID, 3));
2133         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(CPLL_ID, 3));
2134         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(NPLL_ID, 3));
2135
2136         /*wating lock state*/
2137         pll_udelay(168);
2138
2139         pm_pll_wait_lock(APLL_ID);
2140         pm_pll_wait_lock(GPLL_ID);
2141         pm_pll_wait_lock(CPLL_ID);
2142         pm_pll_wait_lock(NPLL_ID);
2143
2144
2145         cru_writel(plls_con3_save[APLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2146                 , RK3288_PLL_CONS(APLL_ID, 3));
2147         cru_writel(plls_con3_save[GPLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2148                 , RK3288_PLL_CONS(GPLL_ID, 3));
2149         cru_writel(plls_con3_save[CPLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2150                 , RK3288_PLL_CONS(CPLL_ID, 3));
2151         cru_writel(plls_con3_save[NPLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2152                 , RK3288_PLL_CONS(NPLL_ID, 3));
2153 }
2154
2155 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
2156
2157 static void pm_plls_suspend(void)
2158 {
2159
2160    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2161    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2162    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2163
2164     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
2165     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
2166     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
2167     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
2168     clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
2169     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
2170     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
2171
2172     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
2173
2174
2175     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
2176     plls_suspend(NPLL_ID);
2177
2178 // cpll
2179     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
2180
2181 // gpll
2182     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
2183
2184     // set 1,pdbus pll is gpll
2185     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
2186
2187     // pd_bus clk
2188     cru_writel(0
2189                         |CRU_W_MSK_SETBITS(0,0,0x7)  //  1  aclk
2190                         |CRU_W_MSK_SETBITS(0,3,0x1f) //  1   aclk src
2191                         |CRU_W_MSK_SETBITS(0,8,0x3) // 1   hclk 0~1 1 2 4
2192                         |CRU_W_MSK_SETBITS(0,12,0x7) //  3   pclk
2193                      , RK3288_CRU_CLKSELS_CON(1));
2194
2195     //crypto for pd_bus
2196     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
2197
2198     // peri aclk hclk pclk
2199     cru_writel(0
2200                         |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2201                         |CRU_W_MSK_SETBITS(0,8,0x3) // 2   hclk 0 1:1,1 2:1 ,2 4:1
2202                         |CRU_W_MSK_SETBITS(0,12,0x3)// 2     0~3  1 2 4 8 div
2203                         , RK3288_CRU_CLKSELS_CON(10));
2204     // pmu alive
2205     cru_writel(CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2206
2207     plls_suspend(CPLL_ID);
2208     plls_suspend(GPLL_ID);
2209
2210 //apll
2211    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2212      // core_m0 core_mp a12_core
2213     cru_writel(0
2214                         |CRU_W_MSK_SETBITS(0,0,0xf) // 1   axi_mo
2215                         |CRU_W_MSK_SETBITS(0,4,0xf) // 3  axi mp
2216                         |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2217                       , RK3288_CRU_CLKSELS_CON(0));
2218     // core0 core1 core2 core3
2219     cru_writel(0
2220                         |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2221                         |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2222                         |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2223                         |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2224                       , RK3288_CRU_CLKSELS_CON(36));
2225     // l2ram atclk pclk
2226     #if 1
2227     cru_writel(0
2228                     |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2229                     |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2230                      |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2231                      , RK3288_CRU_CLKSELS_CON(37));
2232     #else
2233     cru_writel(0
2234                       |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2235                       |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2236                        |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2237                        , RK3288_CRU_CLKSELS_CON(37));
2238     #endif
2239
2240
2241     plls_suspend(APLL_ID);
2242
2243 }
2244
2245 static void pm_plls_resume(void)
2246 {
2247         /* core_m0 core_mp a12_core*/
2248         cru_writel(clk_sel0 | (CRU_W_MSK(0, 0xf) | CRU_W_MSK(4, 0xf)
2249         | CRU_W_MSK(8, 0xf)), RK3288_CRU_CLKSELS_CON(0));
2250         /*core0 core1 core2 core3*/
2251         cru_writel(clk_sel36 | (CRU_W_MSK(0, 0x7) | CRU_W_MSK(4, 0x7)
2252         | CRU_W_MSK(8, 0x7) | CRU_W_MSK(12, 0x7)), RK3288_CRU_CLKSELS_CON(36));
2253         /* l2ram atclk pclk*/
2254         cru_writel(clk_sel37 | (CRU_W_MSK(0, 0x7) | CRU_W_MSK(4, 0x1f)
2255         | CRU_W_MSK(9, 0x1f)), RK3288_CRU_CLKSELS_CON(37));
2256
2257         /*resume APLL_ID GPLL_ID CPLL_ID NPLL_ID*/
2258         plls_resume();
2259
2260         cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(APLL_ID) << 16)
2261                 , RK3288_CRU_MODE_CON);
2262
2263         /*peri aclk hclk pclk*/
2264         cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
2265         | CRU_W_MSK(12, 0x3)), RK3288_CRU_CLKSELS_CON(10));
2266         /*pd bus gpll sel*/
2267         cru_writel(clk_sel1 | CRU_W_MSK(15, 0x1), RK3288_CRU_CLKSELS_CON(1));
2268         /*pd_bus clk 8*/
2269         cru_writel(clk_sel1 | (CRU_W_MSK(0, 0x7) | CRU_W_MSK(3, 0x1f)
2270         | CRU_W_MSK(8, 0x3) | CRU_W_MSK(12, 0x7)), RK3288_CRU_CLKSELS_CON(1));
2271
2272         /*crypto*/
2273         cru_writel(clk_sel26 | CRU_W_MSK(6, 0x3), RK3288_CRU_CLKSELS_CON(26));
2274
2275         /*pmu alive */
2276         cru_writel(clk_sel33 | CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x1f)
2277         , RK3288_CRU_CLKSELS_CON(33));
2278         cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(GPLL_ID) << 16)
2279                 , RK3288_CRU_MODE_CON);
2280         cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(CPLL_ID) << 16)
2281                 , RK3288_CRU_MODE_CON);
2282         cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(NPLL_ID) << 16)
2283                 , RK3288_CRU_MODE_CON);
2284
2285 }
2286
2287 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2288
2289 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2290 {
2291
2292     int div;
2293     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2294     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2295     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2296
2297
2298     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2299     {
2300         div=3;
2301         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2302         cru_writel(0
2303                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2304                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2305                             , RK3288_CRU_MODE_CON);
2306     }
2307     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2308     {
2309         div=31;
2310     }
2311
2312     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2313     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2314     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2315
2316 }
2317
2318 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2319 {
2320
2321     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2322     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2323     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2324     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2325                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2326                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2327                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2328
2329 }
2330
2331
2332 static void clks_gating_suspend_init(void)
2333 {
2334     // get clk gating info
2335     if(rockchip_pie_chunk)
2336         p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2337     else
2338         p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2339     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2340         ==RK3288_CRU_CLKGATES_CON(0))
2341     {
2342         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2343         if(rockchip_pie_chunk)
2344             rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2345                                 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2346
2347         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2348
2349     }
2350     if(rockchip_pie_chunk)
2351         rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2352                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2353 }
2354
2355 /***************************prepare and finish reg_pread***********************************/
2356
2357
2358
2359 #define GIC_DIST_PENDING_SET            0x200
2360 static noinline void rk3288_pm_dump_irq(void)
2361 {
2362         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2363         u32 irq[4];
2364         int i;
2365
2366         for (i = 0; i < ARRAY_SIZE(irq); i++)
2367                 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + (1 + i) * 4);
2368         for (i = 0; i < ARRAY_SIZE(irq); i++) {
2369                 if (irq[i])
2370                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
2371         }
2372         printk("wakeup irq: %08x %08x %08x %08x\n", irq[0], irq[1], irq[2], irq[3]);
2373         for (i = 0; i <= 8; i++) {
2374                 if (irq_gpio & (1 << i))
2375                         printk("wakeup gpio%d: %08x\n", i, readl_relaxed(RK_GPIO_VIRT(i) + GPIO_INT_STATUS));
2376         }
2377 }
2378
2379 #if 0
2380 #define DUMP_GPIO_INTEN(ID) \
2381 do { \
2382         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2383         if (en) { \
2384                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2385                 rkpm_ddr_printhex(en); \
2386                 rkpm_ddr_printch('\n'); \
2387                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2388         } \
2389 } while (0)
2390 #else
2391
2392 #define DUMP_GPIO_INTEN(ID) \
2393     do { \
2394         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2395         if (en) { \
2396                 printk("GPIO%d_INTEN: %08x\n", ID, en); \
2397         } \
2398     } while (0)
2399
2400 #endif
2401
2402
2403 //dump while irq is enable
2404 static noinline void rk3288_pm_dump_inten(void)
2405 {
2406         DUMP_GPIO_INTEN(0);
2407         DUMP_GPIO_INTEN(1);
2408         DUMP_GPIO_INTEN(2);
2409         DUMP_GPIO_INTEN(3);
2410         DUMP_GPIO_INTEN(4);
2411         DUMP_GPIO_INTEN(5);
2412         DUMP_GPIO_INTEN(6);
2413         DUMP_GPIO_INTEN(7);
2414         DUMP_GPIO_INTEN(8);
2415 }
2416
2417 static  void rkpm_prepare(void)
2418 {
2419
2420         int i;
2421          for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2422         {
2423            //cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2424          }
2425
2426         #if 0
2427         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2428
2429        // rkpm_ddr_printhex(temp);
2430         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2431         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2432        // rkpm_ddr_printhex(temp);
2433         #endif
2434         // dump GPIO INTEN for debug
2435         rk3288_pm_dump_inten();
2436 }
2437
2438 static void rkpm_finish(void)
2439 {
2440         rk3288_pm_dump_irq();
2441 }
2442
2443 #if 0
2444 static  void interface_ctr_reg_pread(void)
2445 {
2446         //u32 addr;
2447         flush_cache_all();
2448         outer_flush_all();
2449         local_flush_tlb_all();
2450         #if 0  // do it in ddr suspend
2451         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2452                 readl_relaxed(addr);
2453         #endif
2454         readl_relaxed(RK_PMU_VIRT);
2455         readl_relaxed(RK_GRF_VIRT);
2456         readl_relaxed(RK_DDR_VIRT);
2457         readl_relaxed(RK_GPIO_VIRT(0));
2458         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2459         //readl_relaxed(RK_GPIO_VIRT(3));
2460 }
2461 #endif
2462 void PIE_FUNC(ddr_leakage_tst)(void)
2463 {
2464     cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2465     rkpm_sram_printch('\n');
2466     rkpm_sram_printch('t');
2467     rkpm_sram_printch('e');
2468     rkpm_sram_printch('s');
2469     rkpm_sram_printch('t');
2470     while(1);
2471 }
2472
2473 static void __init  rk3288_suspend_init(void)
2474 {
2475     struct device_node *parent;
2476     u32 pm_ctrbits;
2477
2478     PM_LOG("%s enter\n",__FUNCTION__);
2479
2480     parent = of_find_node_by_name(NULL, "rockchip_suspend");
2481
2482     if (IS_ERR_OR_NULL(parent)) {
2483                 PM_ERR("%s dev node err\n", __func__);
2484                 return;
2485         }
2486
2487
2488     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2489     {
2490             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2491             return ;
2492     }
2493     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2494     pm_io_base_map();
2495     memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2496     rkpm_set_ctrbits(pm_ctrbits);
2497
2498     gpio_get_dts_info(parent);
2499     clks_gating_suspend_init();
2500
2501     rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2502
2503     //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2504
2505     rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2506
2507     //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2508
2509      rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2510      rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2511
2512     if(rockchip_pie_chunk)
2513         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2514
2515     rkpm_set_ops_printch(ddr_printch);
2516 }