Merge tag 'lsk-v3.10-android-14.12'

LSK Android 14.12 v3.10

Conflicts:
	include/linux/clk-provider.h

diff --cc Makefile
Simple merge

diff --cc arch/arm/mm/proc-v7.S
Simple merge

diff --cc arch/arm64/Makefile
Simple merge

diff --cc drivers/acpi/device_pm.c
Simple merge

diff --cc drivers/base/power/domain.c
Simple merge

diff --cc drivers/clk/clk-divider.c
Simple merge

diff --cc drivers/cpufreq/cpufreq_interactive.c
Simple merge

diff --cc include/linux/clk-provider.h
index 6ee9fbf109ef66ceca1424dbd8c8b37036b8f984,89b7ceed70dbb7002b67311f3d35f008440bedb2..90ad8c2f8e064fdc6364f71032d69c7a449c8794
--- 1/include/linux/clk-provider.h
--- 2/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@@ -273,10 -257,8 +273,12 @@@ struct clk_div_table 
   *    Some hardware implementations gracefully handle this case and allow a
   *    zero divisor by not modifying their input clock
   *    (divide by one / bypass).
 + * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
 + *   of this register, and mask of divider bits are in higher 16-bit of this
 + *   register.  While setting the divider bits, higher 16-bit should also be
 + *   updated to indicate changing divider bits.
+  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
+  *    to the closest integer instead of the up one.
   */
  struct clk_divider {
        struct clk_hw   hw;
@@@ -291,7 -273,7 +293,8 @@@
  #define CLK_DIVIDER_ONE_BASED         BIT(0)
  #define CLK_DIVIDER_POWER_OF_TWO      BIT(1)
  #define CLK_DIVIDER_ALLOW_ZERO                BIT(2)
 +#define CLK_DIVIDER_HIWORD_MASK               BIT(3)
+ #define CLK_DIVIDER_ROUND_CLOSEST     BIT(4)
  
  extern const struct clk_ops clk_divider_ops;
  struct clk *clk_register_divider(struct device *dev, const char *name,