drivers/gpu/arm/midgard/mali_kbase_gator_hwcnt_names.h

   1 /*
   2  *
   3  * (C) COPYRIGHT ARM Limited. All rights reserved.
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * A copy of the licence is included with the program, and can also be obtained
  11  * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  12  * Boston, MA  02110-1301, USA.
  13  *
  14  */
  15
  16
  17
  18 #ifndef _KBASE_GATOR_HWCNT_NAMES_H_
  19 #define _KBASE_GATOR_HWCNT_NAMES_H_
  20
  21 /*
  22  * "Short names" for hardware counters used by Streamline. Counters names are
  23  * stored in accordance with their memory layout in the binary counter block
  24  * emitted by the Mali GPU. Each "master" in the GPU emits a fixed-size block
  25  * of 64 counters, and each GPU implements the same set of "masters" although
  26  * the counters each master exposes within its block of 64 may vary.
  27  *
  28  * Counters which are an empty string are simply "holes" in the counter memory
  29  * where no counter exists.
  30  */
  31
  32 static const char * const hardware_counter_names_mali_t60x[] = {
  33         /* Job Manager */
  34         "",
  35         "",
  36         "",
  37         "",
  38         "T60x_MESSAGES_SENT",
  39         "T60x_MESSAGES_RECEIVED",
  40         "T60x_GPU_ACTIVE",
  41         "T60x_IRQ_ACTIVE",
  42         "T60x_JS0_JOBS",
  43         "T60x_JS0_TASKS",
  44         "T60x_JS0_ACTIVE",
  45         "",
  46         "T60x_JS0_WAIT_READ",
  47         "T60x_JS0_WAIT_ISSUE",
  48         "T60x_JS0_WAIT_DEPEND",
  49         "T60x_JS0_WAIT_FINISH",
  50         "T60x_JS1_JOBS",
  51         "T60x_JS1_TASKS",
  52         "T60x_JS1_ACTIVE",
  53         "",
  54         "T60x_JS1_WAIT_READ",
  55         "T60x_JS1_WAIT_ISSUE",
  56         "T60x_JS1_WAIT_DEPEND",
  57         "T60x_JS1_WAIT_FINISH",
  58         "T60x_JS2_JOBS",
  59         "T60x_JS2_TASKS",
  60         "T60x_JS2_ACTIVE",
  61         "",
  62         "T60x_JS2_WAIT_READ",
  63         "T60x_JS2_WAIT_ISSUE",
  64         "T60x_JS2_WAIT_DEPEND",
  65         "T60x_JS2_WAIT_FINISH",
  66         "",
  67         "",
  68         "",
  69         "",
  70         "",
  71         "",
  72         "",
  73         "",
  74         "",
  75         "",
  76         "",
  77         "",
  78         "",
  79         "",
  80         "",
  81         "",
  82         "",
  83         "",
  84         "",
  85         "",
  86         "",
  87         "",
  88         "",
  89         "",
  90         "",
  91         "",
  92         "",
  93         "",
  94         "",
  95         "",
  96         "",
  97         "",
  98
  99         /*Tiler */
 100         "",
 101         "",
 102         "",
 103         "T60x_TI_JOBS_PROCESSED",
 104         "T60x_TI_TRIANGLES",
 105         "T60x_TI_QUADS",
 106         "T60x_TI_POLYGONS",
 107         "T60x_TI_POINTS",
 108         "T60x_TI_LINES",
 109         "T60x_TI_VCACHE_HIT",
 110         "T60x_TI_VCACHE_MISS",
 111         "T60x_TI_FRONT_FACING",
 112         "T60x_TI_BACK_FACING",
 113         "T60x_TI_PRIM_VISIBLE",
 114         "T60x_TI_PRIM_CULLED",
 115         "T60x_TI_PRIM_CLIPPED",
 116         "T60x_TI_LEVEL0",
 117         "T60x_TI_LEVEL1",
 118         "T60x_TI_LEVEL2",
 119         "T60x_TI_LEVEL3",
 120         "T60x_TI_LEVEL4",
 121         "T60x_TI_LEVEL5",
 122         "T60x_TI_LEVEL6",
 123         "T60x_TI_LEVEL7",
 124         "T60x_TI_COMMAND_1",
 125         "T60x_TI_COMMAND_2",
 126         "T60x_TI_COMMAND_3",
 127         "T60x_TI_COMMAND_4",
 128         "T60x_TI_COMMAND_4_7",
 129         "T60x_TI_COMMAND_8_15",
 130         "T60x_TI_COMMAND_16_63",
 131         "T60x_TI_COMMAND_64",
 132         "T60x_TI_COMPRESS_IN",
 133         "T60x_TI_COMPRESS_OUT",
 134         "T60x_TI_COMPRESS_FLUSH",
 135         "T60x_TI_TIMESTAMPS",
 136         "T60x_TI_PCACHE_HIT",
 137         "T60x_TI_PCACHE_MISS",
 138         "T60x_TI_PCACHE_LINE",
 139         "T60x_TI_PCACHE_STALL",
 140         "T60x_TI_WRBUF_HIT",
 141         "T60x_TI_WRBUF_MISS",
 142         "T60x_TI_WRBUF_LINE",
 143         "T60x_TI_WRBUF_PARTIAL",
 144         "T60x_TI_WRBUF_STALL",
 145         "T60x_TI_ACTIVE",
 146         "T60x_TI_LOADING_DESC",
 147         "T60x_TI_INDEX_WAIT",
 148         "T60x_TI_INDEX_RANGE_WAIT",
 149         "T60x_TI_VERTEX_WAIT",
 150         "T60x_TI_PCACHE_WAIT",
 151         "T60x_TI_WRBUF_WAIT",
 152         "T60x_TI_BUS_READ",
 153         "T60x_TI_BUS_WRITE",
 154         "",
 155         "",
 156         "",
 157         "",
 158         "",
 159         "T60x_TI_UTLB_STALL",
 160         "T60x_TI_UTLB_REPLAY_MISS",
 161         "T60x_TI_UTLB_REPLAY_FULL",
 162         "T60x_TI_UTLB_NEW_MISS",
 163         "T60x_TI_UTLB_HIT",
 164
 165         /* Shader Core */
 166         "",
 167         "",
 168         "",
 169         "",
 170         "T60x_FRAG_ACTIVE",
 171         "T60x_FRAG_PRIMITIVES",
 172         "T60x_FRAG_PRIMITIVES_DROPPED",
 173         "T60x_FRAG_CYCLES_DESC",
 174         "T60x_FRAG_CYCLES_PLR",
 175         "T60x_FRAG_CYCLES_VERT",
 176         "T60x_FRAG_CYCLES_TRISETUP",
 177         "T60x_FRAG_CYCLES_RAST",
 178         "T60x_FRAG_THREADS",
 179         "T60x_FRAG_DUMMY_THREADS",
 180         "T60x_FRAG_QUADS_RAST",
 181         "T60x_FRAG_QUADS_EZS_TEST",
 182         "T60x_FRAG_QUADS_EZS_KILLED",
 183         "T60x_FRAG_THREADS_LZS_TEST",
 184         "T60x_FRAG_THREADS_LZS_KILLED",
 185         "T60x_FRAG_CYCLES_NO_TILE",
 186         "T60x_FRAG_NUM_TILES",
 187         "T60x_FRAG_TRANS_ELIM",
 188         "T60x_COMPUTE_ACTIVE",
 189         "T60x_COMPUTE_TASKS",
 190         "T60x_COMPUTE_THREADS",
 191         "T60x_COMPUTE_CYCLES_DESC",
 192         "T60x_TRIPIPE_ACTIVE",
 193         "T60x_ARITH_WORDS",
 194         "T60x_ARITH_CYCLES_REG",
 195         "T60x_ARITH_CYCLES_L0",
 196         "T60x_ARITH_FRAG_DEPEND",
 197         "T60x_LS_WORDS",
 198         "T60x_LS_ISSUES",
 199         "T60x_LS_RESTARTS",
 200         "T60x_LS_REISSUES_MISS",
 201         "T60x_LS_REISSUES_VD",
 202         "T60x_LS_REISSUE_ATTRIB_MISS",
 203         "T60x_LS_NO_WB",
 204         "T60x_TEX_WORDS",
 205         "T60x_TEX_BUBBLES",
 206         "T60x_TEX_WORDS_L0",
 207         "T60x_TEX_WORDS_DESC",
 208         "T60x_TEX_ISSUES",
 209         "T60x_TEX_RECIRC_FMISS",
 210         "T60x_TEX_RECIRC_DESC",
 211         "T60x_TEX_RECIRC_MULTI",
 212         "T60x_TEX_RECIRC_PMISS",
 213         "T60x_TEX_RECIRC_CONF",
 214         "T60x_LSC_READ_HITS",
 215         "T60x_LSC_READ_MISSES",
 216         "T60x_LSC_WRITE_HITS",
 217         "T60x_LSC_WRITE_MISSES",
 218         "T60x_LSC_ATOMIC_HITS",
 219         "T60x_LSC_ATOMIC_MISSES",
 220         "T60x_LSC_LINE_FETCHES",
 221         "T60x_LSC_DIRTY_LINE",
 222         "T60x_LSC_SNOOPS",
 223         "T60x_AXI_TLB_STALL",
 224         "T60x_AXI_TLB_MIESS",
 225         "T60x_AXI_TLB_TRANSACTION",
 226         "T60x_LS_TLB_MISS",
 227         "T60x_LS_TLB_HIT",
 228         "T60x_AXI_BEATS_READ",
 229         "T60x_AXI_BEATS_WRITTEN",
 230
 231         /*L2 and MMU */
 232         "",
 233         "",
 234         "",
 235         "",
 236         "T60x_MMU_HIT",
 237         "T60x_MMU_NEW_MISS",
 238         "T60x_MMU_REPLAY_FULL",
 239         "T60x_MMU_REPLAY_MISS",
 240         "T60x_MMU_TABLE_WALK",
 241         "",
 242         "",
 243         "",
 244         "",
 245         "",
 246         "",
 247         "",
 248         "T60x_UTLB_HIT",
 249         "T60x_UTLB_NEW_MISS",
 250         "T60x_UTLB_REPLAY_FULL",
 251         "T60x_UTLB_REPLAY_MISS",
 252         "T60x_UTLB_STALL",
 253         "",
 254         "",
 255         "",
 256         "",
 257         "",
 258         "",
 259         "",
 260         "",
 261         "",
 262         "T60x_L2_EXT_WRITE_BEATS",
 263         "T60x_L2_EXT_READ_BEATS",
 264         "T60x_L2_ANY_LOOKUP",
 265         "T60x_L2_READ_LOOKUP",
 266         "T60x_L2_SREAD_LOOKUP",
 267         "T60x_L2_READ_REPLAY",
 268         "T60x_L2_READ_SNOOP",
 269         "T60x_L2_READ_HIT",
 270         "T60x_L2_CLEAN_MISS",
 271         "T60x_L2_WRITE_LOOKUP",
 272         "T60x_L2_SWRITE_LOOKUP",
 273         "T60x_L2_WRITE_REPLAY",
 274         "T60x_L2_WRITE_SNOOP",
 275         "T60x_L2_WRITE_HIT",
 276         "T60x_L2_EXT_READ_FULL",
 277         "T60x_L2_EXT_READ_HALF",
 278         "T60x_L2_EXT_WRITE_FULL",
 279         "T60x_L2_EXT_WRITE_HALF",
 280         "T60x_L2_EXT_READ",
 281         "T60x_L2_EXT_READ_LINE",
 282         "T60x_L2_EXT_WRITE",
 283         "T60x_L2_EXT_WRITE_LINE",
 284         "T60x_L2_EXT_WRITE_SMALL",
 285         "T60x_L2_EXT_BARRIER",
 286         "T60x_L2_EXT_AR_STALL",
 287         "T60x_L2_EXT_R_BUF_FULL",
 288         "T60x_L2_EXT_RD_BUF_FULL",
 289         "T60x_L2_EXT_R_RAW",
 290         "T60x_L2_EXT_W_STALL",
 291         "T60x_L2_EXT_W_BUF_FULL",
 292         "T60x_L2_EXT_R_W_HAZARD",
 293         "T60x_L2_TAG_HAZARD",
 294         "T60x_L2_SNOOP_FULL",
 295         "T60x_L2_REPLAY_FULL"
 296 };
 297 static const char * const hardware_counter_names_mali_t62x[] = {
 298         /* Job Manager */
 299         "",
 300         "",
 301         "",
 302         "",
 303         "T62x_MESSAGES_SENT",
 304         "T62x_MESSAGES_RECEIVED",
 305         "T62x_GPU_ACTIVE",
 306         "T62x_IRQ_ACTIVE",
 307         "T62x_JS0_JOBS",
 308         "T62x_JS0_TASKS",
 309         "T62x_JS0_ACTIVE",
 310         "",
 311         "T62x_JS0_WAIT_READ",
 312         "T62x_JS0_WAIT_ISSUE",
 313         "T62x_JS0_WAIT_DEPEND",
 314         "T62x_JS0_WAIT_FINISH",
 315         "T62x_JS1_JOBS",
 316         "T62x_JS1_TASKS",
 317         "T62x_JS1_ACTIVE",
 318         "",
 319         "T62x_JS1_WAIT_READ",
 320         "T62x_JS1_WAIT_ISSUE",
 321         "T62x_JS1_WAIT_DEPEND",
 322         "T62x_JS1_WAIT_FINISH",
 323         "T62x_JS2_JOBS",
 324         "T62x_JS2_TASKS",
 325         "T62x_JS2_ACTIVE",
 326         "",
 327         "T62x_JS2_WAIT_READ",
 328         "T62x_JS2_WAIT_ISSUE",
 329         "T62x_JS2_WAIT_DEPEND",
 330         "T62x_JS2_WAIT_FINISH",
 331         "",
 332         "",
 333         "",
 334         "",
 335         "",
 336         "",
 337         "",
 338         "",
 339         "",
 340         "",
 341         "",
 342         "",
 343         "",
 344         "",
 345         "",
 346         "",
 347         "",
 348         "",
 349         "",
 350         "",
 351         "",
 352         "",
 353         "",
 354         "",
 355         "",
 356         "",
 357         "",
 358         "",
 359         "",
 360         "",
 361         "",
 362         "",
 363
 364         /*Tiler */
 365         "",
 366         "",
 367         "",
 368         "T62x_TI_JOBS_PROCESSED",
 369         "T62x_TI_TRIANGLES",
 370         "T62x_TI_QUADS",
 371         "T62x_TI_POLYGONS",
 372         "T62x_TI_POINTS",
 373         "T62x_TI_LINES",
 374         "T62x_TI_VCACHE_HIT",
 375         "T62x_TI_VCACHE_MISS",
 376         "T62x_TI_FRONT_FACING",
 377         "T62x_TI_BACK_FACING",
 378         "T62x_TI_PRIM_VISIBLE",
 379         "T62x_TI_PRIM_CULLED",
 380         "T62x_TI_PRIM_CLIPPED",
 381         "T62x_TI_LEVEL0",
 382         "T62x_TI_LEVEL1",
 383         "T62x_TI_LEVEL2",
 384         "T62x_TI_LEVEL3",
 385         "T62x_TI_LEVEL4",
 386         "T62x_TI_LEVEL5",
 387         "T62x_TI_LEVEL6",
 388         "T62x_TI_LEVEL7",
 389         "T62x_TI_COMMAND_1",
 390         "T62x_TI_COMMAND_2",
 391         "T62x_TI_COMMAND_3",
 392         "T62x_TI_COMMAND_4",
 393         "T62x_TI_COMMAND_5_7",
 394         "T62x_TI_COMMAND_8_15",
 395         "T62x_TI_COMMAND_16_63",
 396         "T62x_TI_COMMAND_64",
 397         "T62x_TI_COMPRESS_IN",
 398         "T62x_TI_COMPRESS_OUT",
 399         "T62x_TI_COMPRESS_FLUSH",
 400         "T62x_TI_TIMESTAMPS",
 401         "T62x_TI_PCACHE_HIT",
 402         "T62x_TI_PCACHE_MISS",
 403         "T62x_TI_PCACHE_LINE",
 404         "T62x_TI_PCACHE_STALL",
 405         "T62x_TI_WRBUF_HIT",
 406         "T62x_TI_WRBUF_MISS",
 407         "T62x_TI_WRBUF_LINE",
 408         "T62x_TI_WRBUF_PARTIAL",
 409         "T62x_TI_WRBUF_STALL",
 410         "T62x_TI_ACTIVE",
 411         "T62x_TI_LOADING_DESC",
 412         "T62x_TI_INDEX_WAIT",
 413         "T62x_TI_INDEX_RANGE_WAIT",
 414         "T62x_TI_VERTEX_WAIT",
 415         "T62x_TI_PCACHE_WAIT",
 416         "T62x_TI_WRBUF_WAIT",
 417         "T62x_TI_BUS_READ",
 418         "T62x_TI_BUS_WRITE",
 419         "",
 420         "",
 421         "",
 422         "",
 423         "",
 424         "T62x_TI_UTLB_STALL",
 425         "T62x_TI_UTLB_REPLAY_MISS",
 426         "T62x_TI_UTLB_REPLAY_FULL",
 427         "T62x_TI_UTLB_NEW_MISS",
 428         "T62x_TI_UTLB_HIT",
 429
 430         /* Shader Core */
 431         "",
 432         "",
 433         "",
 434         "T62x_SHADER_CORE_ACTIVE",
 435         "T62x_FRAG_ACTIVE",
 436         "T62x_FRAG_PRIMITIVES",
 437         "T62x_FRAG_PRIMITIVES_DROPPED",
 438         "T62x_FRAG_CYCLES_DESC",
 439         "T62x_FRAG_CYCLES_FPKQ_ACTIVE",
 440         "T62x_FRAG_CYCLES_VERT",
 441         "T62x_FRAG_CYCLES_TRISETUP",
 442         "T62x_FRAG_CYCLES_EZS_ACTIVE",
 443         "T62x_FRAG_THREADS",
 444         "T62x_FRAG_DUMMY_THREADS",
 445         "T62x_FRAG_QUADS_RAST",
 446         "T62x_FRAG_QUADS_EZS_TEST",
 447         "T62x_FRAG_QUADS_EZS_KILLED",
 448         "T62x_FRAG_THREADS_LZS_TEST",
 449         "T62x_FRAG_THREADS_LZS_KILLED",
 450         "T62x_FRAG_CYCLES_NO_TILE",
 451         "T62x_FRAG_NUM_TILES",
 452         "T62x_FRAG_TRANS_ELIM",
 453         "T62x_COMPUTE_ACTIVE",
 454         "T62x_COMPUTE_TASKS",
 455         "T62x_COMPUTE_THREADS",
 456         "T62x_COMPUTE_CYCLES_DESC",
 457         "T62x_TRIPIPE_ACTIVE",
 458         "T62x_ARITH_WORDS",
 459         "T62x_ARITH_CYCLES_REG",
 460         "T62x_ARITH_CYCLES_L0",
 461         "T62x_ARITH_FRAG_DEPEND",
 462         "T62x_LS_WORDS",
 463         "T62x_LS_ISSUES",
 464         "T62x_LS_RESTARTS",
 465         "T62x_LS_REISSUES_MISS",
 466         "T62x_LS_REISSUES_VD",
 467         "T62x_LS_REISSUE_ATTRIB_MISS",
 468         "T62x_LS_NO_WB",
 469         "T62x_TEX_WORDS",
 470         "T62x_TEX_BUBBLES",
 471         "T62x_TEX_WORDS_L0",
 472         "T62x_TEX_WORDS_DESC",
 473         "T62x_TEX_ISSUES",
 474         "T62x_TEX_RECIRC_FMISS",
 475         "T62x_TEX_RECIRC_DESC",
 476         "T62x_TEX_RECIRC_MULTI",
 477         "T62x_TEX_RECIRC_PMISS",
 478         "T62x_TEX_RECIRC_CONF",
 479         "T62x_LSC_READ_HITS",
 480         "T62x_LSC_READ_MISSES",
 481         "T62x_LSC_WRITE_HITS",
 482         "T62x_LSC_WRITE_MISSES",
 483         "T62x_LSC_ATOMIC_HITS",
 484         "T62x_LSC_ATOMIC_MISSES",
 485         "T62x_LSC_LINE_FETCHES",
 486         "T62x_LSC_DIRTY_LINE",
 487         "T62x_LSC_SNOOPS",
 488         "T62x_AXI_TLB_STALL",
 489         "T62x_AXI_TLB_MIESS",
 490         "T62x_AXI_TLB_TRANSACTION",
 491         "T62x_LS_TLB_MISS",
 492         "T62x_LS_TLB_HIT",
 493         "T62x_AXI_BEATS_READ",
 494         "T62x_AXI_BEATS_WRITTEN",
 495
 496         /*L2 and MMU */
 497         "",
 498         "",
 499         "",
 500         "",
 501         "T62x_MMU_HIT",
 502         "T62x_MMU_NEW_MISS",
 503         "T62x_MMU_REPLAY_FULL",
 504         "T62x_MMU_REPLAY_MISS",
 505         "T62x_MMU_TABLE_WALK",
 506         "",
 507         "",
 508         "",
 509         "",
 510         "",
 511         "",
 512         "",
 513         "T62x_UTLB_HIT",
 514         "T62x_UTLB_NEW_MISS",
 515         "T62x_UTLB_REPLAY_FULL",
 516         "T62x_UTLB_REPLAY_MISS",
 517         "T62x_UTLB_STALL",
 518         "",
 519         "",
 520         "",
 521         "",
 522         "",
 523         "",
 524         "",
 525         "",
 526         "",
 527         "T62x_L2_EXT_WRITE_BEATS",
 528         "T62x_L2_EXT_READ_BEATS",
 529         "T62x_L2_ANY_LOOKUP",
 530         "T62x_L2_READ_LOOKUP",
 531         "T62x_L2_SREAD_LOOKUP",
 532         "T62x_L2_READ_REPLAY",
 533         "T62x_L2_READ_SNOOP",
 534         "T62x_L2_READ_HIT",
 535         "T62x_L2_CLEAN_MISS",
 536         "T62x_L2_WRITE_LOOKUP",
 537         "T62x_L2_SWRITE_LOOKUP",
 538         "T62x_L2_WRITE_REPLAY",
 539         "T62x_L2_WRITE_SNOOP",
 540         "T62x_L2_WRITE_HIT",
 541         "T62x_L2_EXT_READ_FULL",
 542         "T62x_L2_EXT_READ_HALF",
 543         "T62x_L2_EXT_WRITE_FULL",
 544         "T62x_L2_EXT_WRITE_HALF",
 545         "T62x_L2_EXT_READ",
 546         "T62x_L2_EXT_READ_LINE",
 547         "T62x_L2_EXT_WRITE",
 548         "T62x_L2_EXT_WRITE_LINE",
 549         "T62x_L2_EXT_WRITE_SMALL",
 550         "T62x_L2_EXT_BARRIER",
 551         "T62x_L2_EXT_AR_STALL",
 552         "T62x_L2_EXT_R_BUF_FULL",
 553         "T62x_L2_EXT_RD_BUF_FULL",
 554         "T62x_L2_EXT_R_RAW",
 555         "T62x_L2_EXT_W_STALL",
 556         "T62x_L2_EXT_W_BUF_FULL",
 557         "T62x_L2_EXT_R_W_HAZARD",
 558         "T62x_L2_TAG_HAZARD",
 559         "T62x_L2_SNOOP_FULL",
 560         "T62x_L2_REPLAY_FULL"
 561 };
 562
 563 static const char * const hardware_counter_names_mali_t72x[] = {
 564         /* Job Manager */
 565         "",
 566         "",
 567         "",
 568         "",
 569         "T72x_GPU_ACTIVE",
 570         "T72x_IRQ_ACTIVE",
 571         "T72x_JS0_JOBS",
 572         "T72x_JS0_TASKS",
 573         "T72x_JS0_ACTIVE",
 574         "T72x_JS1_JOBS",
 575         "T72x_JS1_TASKS",
 576         "T72x_JS1_ACTIVE",
 577         "T72x_JS2_JOBS",
 578         "T72x_JS2_TASKS",
 579         "T72x_JS2_ACTIVE",
 580         "",
 581         "",
 582         "",
 583         "",
 584         "",
 585         "",
 586         "",
 587         "",
 588         "",
 589         "",
 590         "",
 591         "",
 592         "",
 593         "",
 594         "",
 595         "",
 596         "",
 597         "",
 598         "",
 599         "",
 600         "",
 601         "",
 602         "",
 603         "",
 604         "",
 605         "",
 606         "",
 607         "",
 608         "",
 609         "",
 610         "",
 611         "",
 612         "",
 613         "",
 614         "",
 615         "",
 616         "",
 617         "",
 618         "",
 619         "",
 620         "",
 621         "",
 622         "",
 623         "",
 624         "",
 625         "",
 626         "",
 627         "",
 628         "",
 629
 630         /*Tiler */
 631         "",
 632         "",
 633         "",
 634         "T72x_TI_JOBS_PROCESSED",
 635         "T72x_TI_TRIANGLES",
 636         "T72x_TI_QUADS",
 637         "T72x_TI_POLYGONS",
 638         "T72x_TI_POINTS",
 639         "T72x_TI_LINES",
 640         "T72x_TI_FRONT_FACING",
 641         "T72x_TI_BACK_FACING",
 642         "T72x_TI_PRIM_VISIBLE",
 643         "T72x_TI_PRIM_CULLED",
 644         "T72x_TI_PRIM_CLIPPED",
 645         "",
 646         "",
 647         "",
 648         "",
 649         "",
 650         "",
 651         "",
 652         "",
 653         "T72x_TI_ACTIVE",
 654         "",
 655         "",
 656         "",
 657         "",
 658         "",
 659         "",
 660         "",
 661         "",
 662         "",
 663         "",
 664         "",
 665         "",
 666         "",
 667         "",
 668         "",
 669         "",
 670         "",
 671         "",
 672         "",
 673         "",
 674         "",
 675         "",
 676         "",
 677         "",
 678         "",
 679         "",
 680         "",
 681         "",
 682         "",
 683         "",
 684         "",
 685         "",
 686         "",
 687         "",
 688         "",
 689         "",
 690         "",
 691         "",
 692         "",
 693         "",
 694         "",
 695
 696         /* Shader Core */
 697         "",
 698         "",
 699         "",
 700         "",
 701         "T72x_FRAG_ACTIVE",
 702         "T72x_FRAG_PRIMITIVES",
 703         "T72x_FRAG_PRIMITIVES_DROPPED",
 704         "T72x_FRAG_THREADS",
 705         "T72x_FRAG_DUMMY_THREADS",
 706         "T72x_FRAG_QUADS_RAST",
 707         "T72x_FRAG_QUADS_EZS_TEST",
 708         "T72x_FRAG_QUADS_EZS_KILLED",
 709         "T72x_FRAG_THREADS_LZS_TEST",
 710         "T72x_FRAG_THREADS_LZS_KILLED",
 711         "T72x_FRAG_CYCLES_NO_TILE",
 712         "T72x_FRAG_NUM_TILES",
 713         "T72x_FRAG_TRANS_ELIM",
 714         "T72x_COMPUTE_ACTIVE",
 715         "T72x_COMPUTE_TASKS",
 716         "T72x_COMPUTE_THREADS",
 717         "T72x_TRIPIPE_ACTIVE",
 718         "T72x_ARITH_WORDS",
 719         "T72x_ARITH_CYCLES_REG",
 720         "T72x_LS_WORDS",
 721         "T72x_LS_ISSUES",
 722         "T72x_LS_RESTARTS",
 723         "T72x_LS_REISSUES_MISS",
 724         "T72x_TEX_WORDS",
 725         "T72x_TEX_BUBBLES",
 726         "T72x_TEX_ISSUES",
 727         "T72x_LSC_READ_HITS",
 728         "T72x_LSC_READ_MISSES",
 729         "T72x_LSC_WRITE_HITS",
 730         "T72x_LSC_WRITE_MISSES",
 731         "T72x_LSC_ATOMIC_HITS",
 732         "T72x_LSC_ATOMIC_MISSES",
 733         "T72x_LSC_LINE_FETCHES",
 734         "T72x_LSC_DIRTY_LINE",
 735         "T72x_LSC_SNOOPS",
 736         "",
 737         "",
 738         "",
 739         "",
 740         "",
 741         "",
 742         "",
 743         "",
 744         "",
 745         "",
 746         "",
 747         "",
 748         "",
 749         "",
 750         "",
 751         "",
 752         "",
 753         "",
 754         "",
 755         "",
 756         "",
 757         "",
 758         "",
 759         "",
 760         "",
 761
 762         /*L2 and MMU */
 763         "",
 764         "",
 765         "",
 766         "",
 767         "T72x_L2_EXT_WRITE_BEAT",
 768         "T72x_L2_EXT_READ_BEAT",
 769         "T72x_L2_READ_SNOOP",
 770         "T72x_L2_READ_HIT",
 771         "T72x_L2_WRITE_SNOOP",
 772         "T72x_L2_WRITE_HIT",
 773         "T72x_L2_EXT_WRITE_SMALL",
 774         "T72x_L2_EXT_BARRIER",
 775         "T72x_L2_EXT_AR_STALL",
 776         "T72x_L2_EXT_W_STALL",
 777         "T72x_L2_SNOOP_FULL",
 778         "",
 779         "",
 780         "",
 781         "",
 782         "",
 783         "",
 784         "",
 785         "",
 786         "",
 787         "",
 788         "",
 789         "",
 790         "",
 791         "",
 792         "",
 793         "",
 794         "",
 795         "",
 796         "",
 797         "",
 798         "",
 799         "",
 800         "",
 801         "",
 802         "",
 803         "",
 804         "",
 805         "",
 806         "",
 807         "",
 808         "",
 809         "",
 810         "",
 811         "",
 812         "",
 813         "",
 814         "",
 815         "",
 816         "",
 817         "",
 818         "",
 819         "",
 820         "",
 821         "",
 822         "",
 823         "",
 824         "",
 825         "",
 826         ""
 827 };
 828
 829 static const char * const hardware_counter_names_mali_t76x[] = {
 830         /* Job Manager */
 831         "",
 832         "",
 833         "",
 834         "",
 835         "T76x_MESSAGES_SENT",
 836         "T76x_MESSAGES_RECEIVED",
 837         "T76x_GPU_ACTIVE",
 838         "T76x_IRQ_ACTIVE",
 839         "T76x_JS0_JOBS",
 840         "T76x_JS0_TASKS",
 841         "T76x_JS0_ACTIVE",
 842         "",
 843         "T76x_JS0_WAIT_READ",
 844         "T76x_JS0_WAIT_ISSUE",
 845         "T76x_JS0_WAIT_DEPEND",
 846         "T76x_JS0_WAIT_FINISH",
 847         "T76x_JS1_JOBS",
 848         "T76x_JS1_TASKS",
 849         "T76x_JS1_ACTIVE",
 850         "",
 851         "T76x_JS1_WAIT_READ",
 852         "T76x_JS1_WAIT_ISSUE",
 853         "T76x_JS1_WAIT_DEPEND",
 854         "T76x_JS1_WAIT_FINISH",
 855         "T76x_JS2_JOBS",
 856         "T76x_JS2_TASKS",
 857         "T76x_JS2_ACTIVE",
 858         "",
 859         "T76x_JS2_WAIT_READ",
 860         "T76x_JS2_WAIT_ISSUE",
 861         "T76x_JS2_WAIT_DEPEND",
 862         "T76x_JS2_WAIT_FINISH",
 863         "",
 864         "",
 865         "",
 866         "",
 867         "",
 868         "",
 869         "",
 870         "",
 871         "",
 872         "",
 873         "",
 874         "",
 875         "",
 876         "",
 877         "",
 878         "",
 879         "",
 880         "",
 881         "",
 882         "",
 883         "",
 884         "",
 885         "",
 886         "",
 887         "",
 888         "",
 889         "",
 890         "",
 891         "",
 892         "",
 893         "",
 894         "",
 895
 896         /*Tiler */
 897         "",
 898         "",
 899         "",
 900         "T76x_TI_JOBS_PROCESSED",
 901         "T76x_TI_TRIANGLES",
 902         "T76x_TI_QUADS",
 903         "T76x_TI_POLYGONS",
 904         "T76x_TI_POINTS",
 905         "T76x_TI_LINES",
 906         "T76x_TI_VCACHE_HIT",
 907         "T76x_TI_VCACHE_MISS",
 908         "T76x_TI_FRONT_FACING",
 909         "T76x_TI_BACK_FACING",
 910         "T76x_TI_PRIM_VISIBLE",
 911         "T76x_TI_PRIM_CULLED",
 912         "T76x_TI_PRIM_CLIPPED",
 913         "T76x_TI_LEVEL0",
 914         "T76x_TI_LEVEL1",
 915         "T76x_TI_LEVEL2",
 916         "T76x_TI_LEVEL3",
 917         "T76x_TI_LEVEL4",
 918         "T76x_TI_LEVEL5",
 919         "T76x_TI_LEVEL6",
 920         "T76x_TI_LEVEL7",
 921         "T76x_TI_COMMAND_1",
 922         "T76x_TI_COMMAND_2",
 923         "T76x_TI_COMMAND_3",
 924         "T76x_TI_COMMAND_4",
 925         "T76x_TI_COMMAND_5_7",
 926         "T76x_TI_COMMAND_8_15",
 927         "T76x_TI_COMMAND_16_63",
 928         "T76x_TI_COMMAND_64",
 929         "T76x_TI_COMPRESS_IN",
 930         "T76x_TI_COMPRESS_OUT",
 931         "T76x_TI_COMPRESS_FLUSH",
 932         "T76x_TI_TIMESTAMPS",
 933         "T76x_TI_PCACHE_HIT",
 934         "T76x_TI_PCACHE_MISS",
 935         "T76x_TI_PCACHE_LINE",
 936         "T76x_TI_PCACHE_STALL",
 937         "T76x_TI_WRBUF_HIT",
 938         "T76x_TI_WRBUF_MISS",
 939         "T76x_TI_WRBUF_LINE",
 940         "T76x_TI_WRBUF_PARTIAL",
 941         "T76x_TI_WRBUF_STALL",
 942         "T76x_TI_ACTIVE",
 943         "T76x_TI_LOADING_DESC",
 944         "T76x_TI_INDEX_WAIT",
 945         "T76x_TI_INDEX_RANGE_WAIT",
 946         "T76x_TI_VERTEX_WAIT",
 947         "T76x_TI_PCACHE_WAIT",
 948         "T76x_TI_WRBUF_WAIT",
 949         "T76x_TI_BUS_READ",
 950         "T76x_TI_BUS_WRITE",
 951         "",
 952         "",
 953         "",
 954         "",
 955         "",
 956         "T76x_TI_UTLB_HIT",
 957         "T76x_TI_UTLB_NEW_MISS",
 958         "T76x_TI_UTLB_REPLAY_FULL",
 959         "T76x_TI_UTLB_REPLAY_MISS",
 960         "T76x_TI_UTLB_STALL",
 961
 962         /* Shader Core */
 963         "",
 964         "",
 965         "",
 966         "",
 967         "T76x_FRAG_ACTIVE",
 968         "T76x_FRAG_PRIMITIVES",
 969         "T76x_FRAG_PRIMITIVES_DROPPED",
 970         "T76x_FRAG_CYCLES_DESC",
 971         "T76x_FRAG_CYCLES_FPKQ_ACTIVE",
 972         "T76x_FRAG_CYCLES_VERT",
 973         "T76x_FRAG_CYCLES_TRISETUP",
 974         "T76x_FRAG_CYCLES_EZS_ACTIVE",
 975         "T76x_FRAG_THREADS",
 976         "T76x_FRAG_DUMMY_THREADS",
 977         "T76x_FRAG_QUADS_RAST",
 978         "T76x_FRAG_QUADS_EZS_TEST",
 979         "T76x_FRAG_QUADS_EZS_KILLED",
 980         "T76x_FRAG_THREADS_LZS_TEST",
 981         "T76x_FRAG_THREADS_LZS_KILLED",
 982         "T76x_FRAG_CYCLES_NO_TILE",
 983         "T76x_FRAG_NUM_TILES",
 984         "T76x_FRAG_TRANS_ELIM",
 985         "T76x_COMPUTE_ACTIVE",
 986         "T76x_COMPUTE_TASKS",
 987         "T76x_COMPUTE_THREADS",
 988         "T76x_COMPUTE_CYCLES_DESC",
 989         "T76x_TRIPIPE_ACTIVE",
 990         "T76x_ARITH_WORDS",
 991         "T76x_ARITH_CYCLES_REG",
 992         "T76x_ARITH_CYCLES_L0",
 993         "T76x_ARITH_FRAG_DEPEND",
 994         "T76x_LS_WORDS",
 995         "T76x_LS_ISSUES",
 996         "T76x_LS_REISSUE_ATTR",
 997         "T76x_LS_REISSUES_VARY",
 998         "T76x_LS_VARY_RV_MISS",
 999         "T76x_LS_VARY_RV_HIT",
1000         "T76x_LS_NO_UNPARK",
1001         "T76x_TEX_WORDS",
1002         "T76x_TEX_BUBBLES",
1003         "T76x_TEX_WORDS_L0",
1004         "T76x_TEX_WORDS_DESC",
1005         "T76x_TEX_ISSUES",
1006         "T76x_TEX_RECIRC_FMISS",
1007         "T76x_TEX_RECIRC_DESC",
1008         "T76x_TEX_RECIRC_MULTI",
1009         "T76x_TEX_RECIRC_PMISS",
1010         "T76x_TEX_RECIRC_CONF",
1011         "T76x_LSC_READ_HITS",
1012         "T76x_LSC_READ_OP",
1013         "T76x_LSC_WRITE_HITS",
1014         "T76x_LSC_WRITE_OP",
1015         "T76x_LSC_ATOMIC_HITS",
1016         "T76x_LSC_ATOMIC_OP",
1017         "T76x_LSC_LINE_FETCHES",
1018         "T76x_LSC_DIRTY_LINE",
1019         "T76x_LSC_SNOOPS",
1020         "T76x_AXI_TLB_STALL",
1021         "T76x_AXI_TLB_MIESS",
1022         "T76x_AXI_TLB_TRANSACTION",
1023         "T76x_LS_TLB_MISS",
1024         "T76x_LS_TLB_HIT",
1025         "T76x_AXI_BEATS_READ",
1026         "T76x_AXI_BEATS_WRITTEN",
1027
1028         /*L2 and MMU */
1029         "",
1030         "",
1031         "",
1032         "",
1033         "T76x_MMU_HIT",
1034         "T76x_MMU_NEW_MISS",
1035         "T76x_MMU_REPLAY_FULL",
1036         "T76x_MMU_REPLAY_MISS",
1037         "T76x_MMU_TABLE_WALK",
1038         "T76x_MMU_REQUESTS",
1039         "",
1040         "",
1041         "T76x_UTLB_HIT",
1042         "T76x_UTLB_NEW_MISS",
1043         "T76x_UTLB_REPLAY_FULL",
1044         "T76x_UTLB_REPLAY_MISS",
1045         "T76x_UTLB_STALL",
1046         "",
1047         "",
1048         "",
1049         "",
1050         "",
1051         "",
1052         "",
1053         "",
1054         "",
1055         "",
1056         "",
1057         "",
1058         "",
1059         "T76x_L2_EXT_WRITE_BEATS",
1060         "T76x_L2_EXT_READ_BEATS",
1061         "T76x_L2_ANY_LOOKUP",
1062         "T76x_L2_READ_LOOKUP",
1063         "T76x_L2_SREAD_LOOKUP",
1064         "T76x_L2_READ_REPLAY",
1065         "T76x_L2_READ_SNOOP",
1066         "T76x_L2_READ_HIT",
1067         "T76x_L2_CLEAN_MISS",
1068         "T76x_L2_WRITE_LOOKUP",
1069         "T76x_L2_SWRITE_LOOKUP",
1070         "T76x_L2_WRITE_REPLAY",
1071         "T76x_L2_WRITE_SNOOP",
1072         "T76x_L2_WRITE_HIT",
1073         "T76x_L2_EXT_READ_FULL",
1074         "",
1075         "T76x_L2_EXT_WRITE_FULL",
1076         "T76x_L2_EXT_R_W_HAZARD",
1077         "T76x_L2_EXT_READ",
1078         "T76x_L2_EXT_READ_LINE",
1079         "T76x_L2_EXT_WRITE",
1080         "T76x_L2_EXT_WRITE_LINE",
1081         "T76x_L2_EXT_WRITE_SMALL",
1082         "T76x_L2_EXT_BARRIER",
1083         "T76x_L2_EXT_AR_STALL",
1084         "T76x_L2_EXT_R_BUF_FULL",
1085         "T76x_L2_EXT_RD_BUF_FULL",
1086         "T76x_L2_EXT_R_RAW",
1087         "T76x_L2_EXT_W_STALL",
1088         "T76x_L2_EXT_W_BUF_FULL",
1089         "T76x_L2_EXT_R_BUF_FULL",
1090         "T76x_L2_TAG_HAZARD",
1091         "T76x_L2_SNOOP_FULL",
1092         "T76x_L2_REPLAY_FULL"
1093 };
1094
1095 #endif