5 #include <linux/ioport.h>
6 #include <linux/kernel.h>
7 #include <linux/math64.h>
8 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/pwm.h>
12 #include <linux/slab.h>
13 #include <linux/types.h>
14 #include <linux/spinlock.h>
15 #include <linux/of_device.h>
16 #include <linux/of_address.h>
17 #include <linux/rockchip/grf.h>
18 #include <linux/rockchip/iomap.h>
21 static int pwm_dbg_level = 0;
22 module_param_named(dbg_level, pwm_dbg_level, int, 0644);
23 #define DBG( args...) \
25 if (pwm_dbg_level) { \
34 #define PWM_REG_CNTR 0x00
35 #define PWM_REG_HRC 0x04
36 #define PWM_REG_LRC 0x08
37 #define PWM_REG_CTRL 0x0c /* PWM Control Register */
39 #define PWM_REG_PERIOD PWM_REG_HRC /* Period Register */
40 #define PWM_REG_DUTY PWM_REG_LRC /* Duty Cycle Register */
42 #define VOP_REG_CNTR 0x0C
43 #define VOP_REG_CTRL 0x00 /* VOP-PWM Control Register */
45 //#define PWM_REG_CTRL 0x0c /* Control Register */
47 #define PWM_DIV_MASK (0xf << 9)
48 #define PWM_CAPTURE (1 << 8)
49 #define PWM_RESET (1 << 7)
50 #define PWM_INTCLR (1 << 6)
51 #define PWM_INTEN (1 << 5)
52 #define PWM_SINGLE (1 << 4)
54 #define PWM_ENABLE (1 << 3)
55 #define PWM_TIMER_EN (1 << 0)
57 #define RK_PWM_DISABLE (0 << 0)
58 #define RK_PWM_ENABLE (1 << 0)
60 #define PWM_SHOT (0 << 1)
61 #define PWM_CONTINUMOUS (1 << 1)
62 #define RK_PWM_CAPTURE (1 << 2)
64 #define PWM_DUTY_POSTIVE (1 << 3)
65 #define PWM_DUTY_NEGATIVE (0 << 3)
67 #define PWM_INACTIVE_POSTIVE (1 << 4)
68 #define PWM_INACTIVE_NEGATIVE (0 << 4)
70 #define PWM_OUTPUT_LEFT (0 << 5)
71 #define PWM_OUTPUT_ENTER (1 << 5)
73 #define PWM_LP_ENABLE (1<<8)
74 #define PWM_LP_DISABLE (0<<8)
76 #define DW_PWM_PRESCALE 9
77 #define RK_PWM_PRESCALE 16
79 #define PWMCR_MIN_PRESCALE 0x00
81 #define PWMCR_MIN_PRESCALE 0x00
82 #define PWMCR_MAX_PRESCALE 0x07
84 #define PWMDCR_MIN_DUTY 0x0000
85 #define PWMDCR_MAX_DUTY 0xFFFF
87 #define PWMPCR_MIN_PERIOD 0x0001
88 #define PWMPCR_MAX_PERIOD 0xFFFF
90 /********************************************
91 * struct rk_pwm_chip - struct representing pwm chip
93 * @base: base address of pwm chip
94 * @clk: pointer to clk structure of pwm chip
95 * @chip: linux pwm chip representation
96 *********************************************/
100 struct clk *aclk_lcdc;
101 struct clk *hclk_lcdc;
102 struct pwm_chip chip;
109 int (*config)(struct pwm_chip *chip,
110 struct pwm_device *pwm, int duty_ns, int period_ns);
111 void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
112 void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
113 void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
117 static inline struct rk_pwm_chip *to_rk_pwm_chip(struct pwm_chip *chip)
119 return container_of(chip, struct rk_pwm_chip, chip);
122 static inline u32 rk_pwm_readl(struct rk_pwm_chip *chip, unsigned int num,
123 unsigned long offset)
125 return readl_relaxed(chip->base + (num << 4) + offset);
128 static inline void rk_pwm_writel(struct rk_pwm_chip *chip,
129 unsigned int num, unsigned long offset,
132 writel_relaxed(val, chip->base + (num << 4) + offset);
135 /* config for rockchip,pwm*/
136 static int rk_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
137 int duty_ns, int period_ns)
139 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
140 u64 val, div, clk_rate;
141 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
147 lock =(&pc->lock);// &pwm_lock[pwm->hwpwm];
149 on = PWM_ENABLE | PWM_TIMER_EN;
151 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
152 * according to formulas described below:
154 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
155 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
157 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
158 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
161 clk_rate = clk_get_rate(pc->clk);
168 val = clk_rate * period_ns;
169 pv = div64_u64(val, div);
170 val = clk_rate * duty_ns;
171 dc = div64_u64(val, div);
173 /* if duty_ns and period_ns are not achievable then return */
174 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
178 * if pv and dc have crossed their upper limit, then increase
179 * prescale and recalculate pv and dc.
181 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
182 if (++prescale > PWMCR_MAX_PRESCALE)
189 /* NOTE: the clock to PWM has to be enabled first before writing to the registers. */
191 spin_lock_irqsave(lock, flags);
193 conf |= (prescale << DW_PWM_PRESCALE);
195 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
197 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,dc);//0x1900);// dc);
198 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pv);//0x5dc0);//pv);
199 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
201 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
203 spin_unlock_irqrestore(lock, flags);
206 static void rk_pwm_set_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
208 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
211 val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
217 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
220 static void rk_pwm_suspend_v1(struct pwm_chip *chip, struct pwm_device *pwm)
222 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
223 pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
224 pc->pwm_duty= rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_HRC);//0x1900);// dc);
225 pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_LRC );//0x5dc0);//pv);
226 pc->pwm_count= rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
228 static void rk_pwm_resume_v1(struct pwm_chip *chip, struct pwm_device *pwm)
230 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
233 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
235 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,pc->pwm_duty);//0x1900);// dc);
236 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pc->pwm_period);//0x5dc0);//pv);
237 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
239 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
241 /* config for rockchip,pwm*/
242 static int rk_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
243 int duty_ns, int period_ns)
245 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
246 u64 val, div, clk_rate;
247 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
253 lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
255 conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
256 PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
258 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
259 * according to formulas described below:
261 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
262 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
264 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
265 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
268 clk_rate = clk_get_rate(pc->clk);
275 val = clk_rate * period_ns;
276 pv = div64_u64(val, div);
277 val = clk_rate * duty_ns;
278 dc = div64_u64(val, div);
280 /* if duty_ns and period_ns are not achievable then return */
281 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
285 * if pv and dc have crossed their upper limit, then increase
286 * prescale and recalculate pv and dc.
288 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
289 if (++prescale > PWMCR_MAX_PRESCALE)
297 * NOTE: the clock to PWM has to be enabled first before writing to the
300 spin_lock_irqsave(lock, flags);
302 conf |= (prescale << RK_PWM_PRESCALE);
304 //rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
306 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc);//0x1900);// dc);
307 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv);//0x5dc0);//pv);
308 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
310 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
311 spin_unlock_irqrestore(lock, flags);
316 static void rk_pwm_set_enable_v2(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
318 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
321 val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
323 val |= RK_PWM_ENABLE;
325 val &= ~RK_PWM_ENABLE;
326 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
327 DBG("%s %d \n", __FUNCTION__, rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL));
332 static void rk_pwm_suspend_v2(struct pwm_chip *chip, struct pwm_device *pwm)
334 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
335 pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
336 pc->pwm_duty = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
337 pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_PERIOD );//0x5dc0);//pv);
338 pc->pwm_count = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
340 static void rk_pwm_resume_v2(struct pwm_chip *chip, struct pwm_device *pwm)
342 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
344 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY, pc->pwm_duty);//0x1900);// dc);
345 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
346 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
348 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
351 /* config for rockchip,pwm*/
352 static int rk_pwm_config_v3(struct pwm_chip *chip, struct pwm_device *pwm,
353 int duty_ns, int period_ns)
355 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
356 u64 val, div, clk_rate;
357 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
363 lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
365 conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
366 PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
368 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
369 * according to formulas described below:
371 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
372 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
374 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
375 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
378 clk_rate = clk_get_rate(pc->clk);
385 val = clk_rate * period_ns;
386 pv = div64_u64(val, div);
387 val = clk_rate * duty_ns;
388 dc = div64_u64(val, div);
390 /* if duty_ns and period_ns are not achievable then return */
391 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
395 * if pv and dc have crossed their upper limit, then increase
396 * prescale and recalculate pv and dc.
398 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
399 if (++prescale > PWMCR_MAX_PRESCALE)
407 * NOTE: the clock to PWM has to be enabled first before writing to the
411 ret = clk_enable(pc->clk);
415 spin_lock_irqsave(lock, flags);
417 conf |= (prescale << RK_PWM_PRESCALE);
420 // rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,off);
423 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc); // 2 0x1900);// dc);
424 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv); // 4 0x5dc0);//pv);
425 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,0);
427 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,on|conf);
429 spin_unlock_irqrestore(lock, flags);
433 static void rk_pwm_set_enable_v3(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
435 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
438 val = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL);
440 val |= RK_PWM_ENABLE;
442 val &= ~RK_PWM_ENABLE;
443 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL, val);
446 static void rk_pwm_suspend_v3(struct pwm_chip *chip, struct pwm_device *pwm)
448 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
449 pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL);
450 pc->pwm_duty = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
451 pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_PERIOD );//0x5dc0);//pv);
452 pc->pwm_count = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CNTR);
454 static void rk_pwm_resume_v3(struct pwm_chip *chip, struct pwm_device *pwm)
456 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
458 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY, pc->pwm_duty);//0x1900);// dc);
459 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
460 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,pc->pwm_count);
462 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,pc->pwm_ctrl);
466 static int rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
467 int duty_ns, int period_ns)
469 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
472 ret = clk_enable(pc->clk);
477 ret = clk_enable(pc->aclk_lcdc);
482 ret = clk_enable(pc->hclk_lcdc);
487 ret = pc->config(chip, pwm, duty_ns, period_ns);
490 clk_disable(pc->aclk_lcdc);
492 clk_disable(pc->hclk_lcdc);
494 clk_disable(pc->clk);
498 static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
500 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
503 ret = clk_enable(pc->clk);
508 ret = clk_enable(pc->aclk_lcdc);
513 ret = clk_enable(pc->hclk_lcdc);
518 pc->set_enable(chip, pwm,true);
522 static void rk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
524 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
526 pc->set_enable(chip, pwm,false);
529 clk_disable(pc->aclk_lcdc);
531 clk_disable(pc->hclk_lcdc);
533 clk_disable(pc->clk);
537 static const struct pwm_ops rk_pwm_ops = {
538 .config = rk_pwm_config,
539 .enable = rk_pwm_enable,
540 .disable = rk_pwm_disable,
541 .owner = THIS_MODULE,
545 int (*config)(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns);
546 void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
547 void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
548 void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
553 static struct rk_pwm_data rk_pwm_data_v1={
554 .config = rk_pwm_config_v1,
555 .set_enable = rk_pwm_set_enable_v1,
556 .pwm_suspend = rk_pwm_suspend_v1,
557 .pwm_resume = rk_pwm_resume_v1,
561 static struct rk_pwm_data rk_pwm_data_v2={
562 .config = rk_pwm_config_v2,
563 .set_enable = rk_pwm_set_enable_v2,
564 .pwm_suspend = rk_pwm_suspend_v2,
565 .pwm_resume = rk_pwm_resume_v2,
569 static struct rk_pwm_data rk_pwm_data_v3={
570 .config = rk_pwm_config_v3,
571 .set_enable = rk_pwm_set_enable_v3,
572 .pwm_suspend = rk_pwm_suspend_v3,
573 .pwm_resume = rk_pwm_resume_v3,
577 static const struct of_device_id rk_pwm_of_match[] = {
578 { .compatible = "rockchip,pwm", .data = &rk_pwm_data_v1,},
579 { .compatible = "rockchip,rk-pwm", .data = &rk_pwm_data_v2,},
580 { .compatible = "rockchip,vop-pwm", .data = &rk_pwm_data_v3,},
584 MODULE_DEVICE_TABLE(of, rk_pwm_of_match);
585 static int rk_pwm_probe(struct platform_device *pdev)
587 const struct of_device_id *of_id =
588 of_match_device(rk_pwm_of_match, &pdev->dev);
589 struct device_node *np = pdev->dev.of_node;
590 const struct rk_pwm_data *data;
591 struct rk_pwm_chip *pc;
595 dev_err(&pdev->dev, "failed to match device\n");
598 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
600 dev_err(&pdev->dev, "failed to allocate memory\n");
604 pc->base = of_iomap(np, 0);
605 if (IS_ERR(pc->base)) {
606 printk("PWM base ERR \n");
607 return PTR_ERR(pc->base);
609 pc->clk = devm_clk_get(&pdev->dev, "pclk_pwm");
611 return PTR_ERR(pc->clk);
613 if (of_device_is_compatible(np, "rockchip,vop-pwm")) {
614 pc->aclk_lcdc = devm_clk_get(&pdev->dev, "aclk_lcdc");
615 if (IS_ERR(pc->aclk_lcdc))
616 return PTR_ERR(pc->aclk_lcdc);
618 pc->hclk_lcdc = devm_clk_get(&pdev->dev, "hclk_lcdc");
619 if (IS_ERR(pc->hclk_lcdc))
620 return PTR_ERR(pc->hclk_lcdc);
622 ret = clk_prepare(pc->aclk_lcdc);
625 clk_prepare(pc->hclk_lcdc);
630 platform_set_drvdata(pdev, pc);
632 pc->config = data->config;
633 pc->set_enable = data->set_enable;
634 pc->pwm_suspend = data->pwm_suspend;
635 pc->pwm_resume = data->pwm_resume;
636 pc->chip.dev = &pdev->dev;
637 pc->chip.ops = &rk_pwm_ops;
639 pc->chip.npwm = NUM_PWM;
640 spin_lock_init(&pc->lock);
641 ret = clk_prepare(pc->clk);
645 /* Following enables PWM chip, channels would still
646 be enabled individually through their control register */
647 DBG("npwm = %d, of_pwm_ncells =%d \n"
648 , pc->chip.npwm, pc->chip.of_pwm_n_cells);
649 ret = pwmchip_add(&pc->chip);
651 printk("failed to add pwm\n");
655 DBG("%s end \n",__FUNCTION__);
659 //(struct platform_device *, pm_message_t state);
660 static int rk_pwm_suspend(struct platform_device *pdev, pm_message_t state)
662 struct pwm_device *pwm;
663 struct rk_pwm_chip *pc;
664 struct pwm_chip *chip;
666 pc = platform_get_drvdata(pdev);
670 pc->pwm_suspend(chip,pwm);
672 return 0;//pwmchip_remove(&pc->chip);
674 static int rk_pwm_resume(struct platform_device *pdev)
676 struct pwm_device *pwm;
677 struct rk_pwm_chip *pc;
678 struct pwm_chip *chip;
680 pc = platform_get_drvdata(pdev);
684 pc->pwm_resume(chip,pwm);
685 return 0;//pwmchip_remove(&pc->chip);
688 static int rk_pwm_remove(struct platform_device *pdev)
690 return 0;//pwmchip_remove(&pc->chip);
693 static struct platform_driver rk_pwm_driver = {
696 .of_match_table = rk_pwm_of_match,
698 .probe = rk_pwm_probe,
699 .remove = rk_pwm_remove,
702 module_platform_driver(rk_pwm_driver);
704 MODULE_LICENSE("GPL");
705 MODULE_AUTHOR("<xsf@rock-chips.com>");
706 MODULE_ALIAS("platform:rk-pwm");