1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 FTOSI, // FP to sint within a FP register.
69 FTOUI, // FP to uint within a FP register.
70 SITOF, // sint to FP within a FP register.
71 UITOF, // uint to FP within a FP register.
73 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
74 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
75 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
77 ADDC, // Add with carry
78 ADDE, // Add using carry
79 SUBC, // Sub with carry
80 SUBE, // Sub using carry
82 VMOVRRD, // double to two gprs.
83 VMOVDRR, // Two gprs to double.
85 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
86 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
88 TC_RETURN, // Tail call return pseudo.
92 DYN_ALLOC, // Dynamic allocation on the stack.
94 MEMBARRIER_MCR, // Memory barrier (MCR)
98 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
100 VCEQ, // Vector compare equal.
101 VCEQZ, // Vector compare equal to zero.
102 VCGE, // Vector compare greater than or equal.
103 VCGEZ, // Vector compare greater than or equal to zero.
104 VCLEZ, // Vector compare less than or equal to zero.
105 VCGEU, // Vector compare unsigned greater than or equal.
106 VCGT, // Vector compare greater than.
107 VCGTZ, // Vector compare greater than zero.
108 VCLTZ, // Vector compare less than zero.
109 VCGTU, // Vector compare unsigned greater than.
110 VTST, // Vector test bits.
112 // Vector shift by immediate:
114 VSHRs, // ...right (signed)
115 VSHRu, // ...right (unsigned)
117 // Vector rounding shift by immediate:
118 VRSHRs, // ...right (signed)
119 VRSHRu, // ...right (unsigned)
120 VRSHRN, // ...right narrow
122 // Vector saturating shift by immediate:
123 VQSHLs, // ...left (signed)
124 VQSHLu, // ...left (unsigned)
125 VQSHLsu, // ...left (signed to unsigned)
126 VQSHRNs, // ...right narrow (signed)
127 VQSHRNu, // ...right narrow (unsigned)
128 VQSHRNsu, // ...right narrow (signed to unsigned)
130 // Vector saturating rounding shift by immediate:
131 VQRSHRNs, // ...right narrow (signed)
132 VQRSHRNu, // ...right narrow (unsigned)
133 VQRSHRNsu, // ...right narrow (signed to unsigned)
135 // Vector shift and insert:
139 // Vector get lane (VMOV scalar to ARM core register)
140 // (These are used for 8- and 16-bit element types only.)
141 VGETLANEu, // zero-extend vector extract element
142 VGETLANEs, // sign-extend vector extract element
144 // Vector move immediate and move negated immediate:
148 // Vector move f32 immediate:
157 VREV64, // reverse elements within 64-bit doublewords
158 VREV32, // reverse elements within 32-bit words
159 VREV16, // reverse elements within 16-bit halfwords
160 VZIP, // zip (interleave)
161 VUZP, // unzip (deinterleave)
163 VTBL1, // 1-register shuffle with mask
164 VTBL2, // 2-register shuffle with mask
166 // Vector multiply long:
168 VMULLu, // ...unsigned
170 UMLAL, // 64bit Unsigned Accumulate Multiply
171 SMLAL, // 64bit Signed Accumulate Multiply
173 // Operands of the standard BUILD_VECTOR node are not legalized, which
174 // is fine if BUILD_VECTORs are always lowered to shuffles or other
175 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
176 // operands need to be legalized. Define an ARM-specific version of
177 // BUILD_VECTOR for this purpose.
180 // Floating-point max and min:
189 // Vector OR with immediate
191 // Vector AND with NOT of immediate
194 // Vector bitwise select
197 // Vector load N-element structure to all lanes:
198 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
202 // NEON loads with post-increment base updates:
214 // NEON stores with post-increment base updates:
225 /// Define some predicates that are used for node matching.
227 bool isBitFieldInvertedMask(unsigned v);
230 //===--------------------------------------------------------------------===//
231 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
233 class ARMTargetLowering : public TargetLowering {
235 explicit ARMTargetLowering(const TargetMachine &TM,
236 const ARMSubtarget &STI);
238 unsigned getJumpTableEncoding() const override;
240 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
242 /// ReplaceNodeResults - Replace the results of node with an illegal result
243 /// type with new values built out of custom code.
245 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
246 SelectionDAG &DAG) const override;
248 const char *getTargetNodeName(unsigned Opcode) const override;
250 bool isSelectSupported(SelectSupportKind Kind) const override {
251 // ARM does not support scalar condition selects on vectors.
252 return (Kind != ScalarCondVectorVal);
255 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
256 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
259 EmitInstrWithCustomInserter(MachineInstr *MI,
260 MachineBasicBlock *MBB) const override;
262 void AdjustInstrPostInstrSelection(MachineInstr *MI,
263 SDNode *Node) const override;
265 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
266 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
268 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
270 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
271 /// unaligned memory accesses of the specified type. Returns whether it
272 /// is "fast" by reference in the second argument.
273 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
275 bool *Fast) const override;
277 EVT getOptimalMemOpType(uint64_t Size,
278 unsigned DstAlign, unsigned SrcAlign,
279 bool IsMemset, bool ZeroMemset,
281 MachineFunction &MF) const override;
283 using TargetLowering::isZExtFree;
284 bool isZExtFree(SDValue Val, EVT VT2) const override;
286 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
288 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
291 /// isLegalAddressingMode - Return true if the addressing mode represented
292 /// by AM is legal for this target, for a load/store of the specified type.
293 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
294 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
296 /// isLegalICmpImmediate - Return true if the specified immediate is legal
297 /// icmp immediate, that is the target has icmp instructions which can
298 /// compare a register against the immediate without having to materialize
299 /// the immediate into a register.
300 bool isLegalICmpImmediate(int64_t Imm) const override;
302 /// isLegalAddImmediate - Return true if the specified immediate is legal
303 /// add immediate, that is the target has add instructions which can
304 /// add a register and the immediate without having to materialize
305 /// the immediate into a register.
306 bool isLegalAddImmediate(int64_t Imm) const override;
308 /// getPreIndexedAddressParts - returns true by value, base pointer and
309 /// offset pointer and addressing mode by reference if the node's address
310 /// can be legally represented as pre-indexed load / store address.
311 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
312 ISD::MemIndexedMode &AM,
313 SelectionDAG &DAG) const override;
315 /// getPostIndexedAddressParts - returns true by value, base pointer and
316 /// offset pointer and addressing mode by reference if this node can be
317 /// combined with a load / store to form a post-indexed load / store.
318 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
319 SDValue &Offset, ISD::MemIndexedMode &AM,
320 SelectionDAG &DAG) const override;
322 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
324 const SelectionDAG &DAG,
325 unsigned Depth) const override;
328 bool ExpandInlineAsm(CallInst *CI) const override;
331 getConstraintType(const std::string &Constraint) const override;
333 /// Examine constraint string and operand type and determine a weight value.
334 /// The operand object must already have been set up with the operand type.
335 ConstraintWeight getSingleConstraintMatchWeight(
336 AsmOperandInfo &info, const char *constraint) const override;
338 std::pair<unsigned, const TargetRegisterClass *>
339 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
340 const std::string &Constraint,
341 MVT VT) const override;
343 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
344 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
345 /// true it means one of the asm constraint of the inline asm instruction
346 /// being processed is 'm'.
347 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
348 std::vector<SDValue> &Ops,
349 SelectionDAG &DAG) const override;
351 const ARMSubtarget* getSubtarget() const {
355 /// getRegClassFor - Return the register class that should be used for the
356 /// specified value type.
357 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
359 /// Returns true if a cast between SrcAS and DestAS is a noop.
360 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
361 // Addrspacecasts are always noops.
365 /// createFastISel - This method returns a target specific FastISel object,
366 /// or null if the target does not support "fast" ISel.
367 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
368 const TargetLibraryInfo *libInfo) const override;
370 Sched::Preference getSchedulingPreference(SDNode *N) const override;
373 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
374 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
376 /// isFPImmLegal - Returns true if the target can instruction select the
377 /// specified FP immediate natively. If false, the legalizer will
378 /// materialize the FP immediate as a load from a constant pool.
379 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
381 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
383 unsigned Intrinsic) const override;
385 /// \brief Returns true if it is beneficial to convert a load of a constant
386 /// to just the constant itself.
387 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
388 Type *Ty) const override;
390 /// \brief Returns true if an argument of type Ty needs to be passed in a
391 /// contiguous block of registers in calling convention CallConv.
392 bool functionArgumentNeedsConsecutiveRegisters(
393 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
395 bool hasLoadLinkedStoreConditional() const override;
396 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
397 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
398 AtomicOrdering Ord) const override;
399 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
400 Value *Addr, AtomicOrdering Ord) const override;
402 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
403 bool IsStore, bool IsLoad) const override;
404 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
405 bool IsStore, bool IsLoad) const override;
407 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
408 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
409 TargetLoweringBase::AtomicRMWExpansionKind
410 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
412 bool useLoadStackGuardNode() const override;
414 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
415 unsigned &Cost) const override;
418 std::pair<const TargetRegisterClass *, uint8_t>
419 findRepresentativeClass(const TargetRegisterInfo *TRI,
420 MVT VT) const override;
423 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
424 /// make the right decision when generating code for different targets.
425 const ARMSubtarget *Subtarget;
427 const TargetRegisterInfo *RegInfo;
429 const InstrItineraryData *Itins;
431 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
433 unsigned ARMPCLabelIndex;
435 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
436 void addDRTypeForNEON(MVT VT);
437 void addQRTypeForNEON(MVT VT);
438 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
440 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
441 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
442 SDValue Chain, SDValue &Arg,
443 RegsToPassVector &RegsToPass,
444 CCValAssign &VA, CCValAssign &NextVA,
446 SmallVectorImpl<SDValue> &MemOpChains,
447 ISD::ArgFlagsTy Flags) const;
448 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
449 SDValue &Root, SelectionDAG &DAG,
452 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
453 bool isVarArg) const;
454 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
455 bool isVarArg) const;
456 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
457 SDLoc dl, SelectionDAG &DAG,
458 const CCValAssign &VA,
459 ISD::ArgFlagsTy Flags) const;
460 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
463 const ARMSubtarget *Subtarget) const;
464 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
467 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
468 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
469 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
470 SelectionDAG &DAG) const;
471 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
473 TLSModel::Model model) const;
474 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
487 const ARMSubtarget *ST) const;
488 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
489 const ARMSubtarget *ST) const;
490 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
498 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
500 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
501 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
502 /// expanded to FMAs when this method returns true, otherwise fmuladd is
503 /// expanded to fmul + fadd.
505 /// ARM supports both fused and unfused multiply-add operations; we already
506 /// lower a pair of fmul and fadd to the latter so it's not clear that there
507 /// would be a gain or that the gain would be worthwhile enough to risk
508 /// correctness bugs.
509 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
511 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
513 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
514 CallingConv::ID CallConv, bool isVarArg,
515 const SmallVectorImpl<ISD::InputArg> &Ins,
516 SDLoc dl, SelectionDAG &DAG,
517 SmallVectorImpl<SDValue> &InVals,
518 bool isThisReturn, SDValue ThisVal) const;
521 LowerFormalArguments(SDValue Chain,
522 CallingConv::ID CallConv, bool isVarArg,
523 const SmallVectorImpl<ISD::InputArg> &Ins,
524 SDLoc dl, SelectionDAG &DAG,
525 SmallVectorImpl<SDValue> &InVals) const override;
527 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
528 SDLoc dl, SDValue &Chain,
529 const Value *OrigArg,
530 unsigned InRegsParamRecordIdx,
532 unsigned ArgSize) const;
534 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
535 SDLoc dl, SDValue &Chain,
537 unsigned TotalArgRegsSaveSize,
538 bool ForceMutable = false) const;
541 LowerCall(TargetLowering::CallLoweringInfo &CLI,
542 SmallVectorImpl<SDValue> &InVals) const override;
544 /// HandleByVal - Target-specific cleanup for ByVal support.
545 void HandleByVal(CCState *, unsigned &, unsigned) const override;
547 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
548 /// for tail call optimization. Targets which want to do tail call
549 /// optimization should implement this function.
550 bool IsEligibleForTailCallOptimization(SDValue Callee,
551 CallingConv::ID CalleeCC,
553 bool isCalleeStructRet,
554 bool isCallerStructRet,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
556 const SmallVectorImpl<SDValue> &OutVals,
557 const SmallVectorImpl<ISD::InputArg> &Ins,
558 SelectionDAG& DAG) const;
560 bool CanLowerReturn(CallingConv::ID CallConv,
561 MachineFunction &MF, bool isVarArg,
562 const SmallVectorImpl<ISD::OutputArg> &Outs,
563 LLVMContext &Context) const override;
566 LowerReturn(SDValue Chain,
567 CallingConv::ID CallConv, bool isVarArg,
568 const SmallVectorImpl<ISD::OutputArg> &Outs,
569 const SmallVectorImpl<SDValue> &OutVals,
570 SDLoc dl, SelectionDAG &DAG) const override;
572 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
574 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
576 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
577 SDValue ARMcc, SDValue CCR, SDValue Cmp,
578 SelectionDAG &DAG) const;
579 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
580 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
581 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
582 SelectionDAG &DAG, SDLoc dl) const;
583 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
585 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
587 void SetupEntryBlockForSjLj(MachineInstr *MI,
588 MachineBasicBlock *MBB,
589 MachineBasicBlock *DispatchBB, int FI) const;
591 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
592 MachineBasicBlock *MBB) const;
594 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
596 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
597 MachineBasicBlock *MBB) const;
599 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
600 MachineBasicBlock *MBB) const;
603 enum NEONModImmType {
610 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
611 const TargetLibraryInfo *libInfo);
615 #endif // ARMISELLOWERING_H