[AArch64][FastISel] Variant of the logical instructions that use two input

registers cannot write on SP.

rdar://problem/20748715

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236352 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp
index c70b17c8a32c41e3af137c70a1e141f32a68fe3e..c9fbc85b69896dde6d0555f240ce16b60d931732 100644 (file)
--- a/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/lib/Target/AArch64/AArch64FastISel.cpp
@@ -2573,7 +2573,7 @@ bool AArch64FastISel::optimizeSelect(const SelectInst *SI) {
     Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
     Src1IsKill = true;
   }
-  unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg,
+  unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
                                        Src1IsKill, Src2Reg, Src2IsKill);
   updateValueMap(SI, ResultReg);
   return true;

diff --git a/test/CodeGen/AArch64/arm64-fast-isel.ll b/test/CodeGen/AArch64/arm64-fast-isel.ll
index 6663c9ac577ed71a9043557bf6d2fd24929b1907..9f83a9c359a2b03b271d23218bd75361af66f13b 100644 (file)
--- a/test/CodeGen/AArch64/arm64-fast-isel.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel.ll
@@ -114,3 +114,22 @@ entry:
 }
 
 declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
+
+define void @logicalReg() {
+; Make sure we generate a logical reg = reg, reg instruction without any
+; machine verifier errors.
+; CHECK-LABEL: logicalReg:
+; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: ret
+entry:
+  br i1 undef, label %cond.end, label %cond.false
+
+cond.false:
+  %cond = select i1 undef, i1 true, i1 false
+  br label %cond.end
+
+cond.end:
+  %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
+  ret void
+}
+