ARM64: dts: rk3328: add vop display node

Change-Id: I60322993b782a6d04ca7e46fdc114a0fbc43778a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index cc48cedcea6de2fc0522a719739ea133392d0d18..a84fb713c85b56673429ba83459b34c4a0c10dbb 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -525,6 +525,38 @@
                status = "disabled";
        };
 
+       vop: vop@ff370000 {
+               compatible = "rockchip,rk3328-vop";
+               reg = <0x0 0xff370000 0x0 0x3efc>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+               reset-names = "axi", "ahb", "dclk";
+               iommus = <&vop_mmu>;
+               status = "disabled";
+
+               vop_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
+       vop_mmu: iommu@ff373f00 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff373f00 0x0 0x100>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "vop_mmu";
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       display_subsystem: display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vop_out>;
+               status = "disabled";
+       };
+
        cru: clock-controller@ff440000 {
                compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
                reg = <0x0 0xff440000 0x0 0x1000>;