drm/rockchip: support rk3328 vop

Change-Id: Ic8c1073a22b62fc9a1b2e758429298538727c20e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 9f89c110fa7b904432d5b43e3ee4b4a577d295a3..3c97af58d2d187501e4fb7af2e9db823e879f29c 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -550,6 +550,83 @@ static const struct vop_data rk322x_vop = {
        .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 };
 
+static const struct vop_ctrl rk3328_ctrl_data = {
+       .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
+       .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
+       .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
+       .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
+       .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
+       .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
+       .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
+       .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
+       .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
+       .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
+       .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
+       .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
+       .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
+       .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
+       .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
+       .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
+       .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
+       .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
+       .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
+       .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
+       .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
+       .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
+       .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16),
+       .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20),
+       .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24),
+       .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28),
+
+       .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
+       .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
+
+       .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
+       .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
+       .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
+       .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
+       .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
+
+       .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
+       .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
+
+       .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
+
+       .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
+};
+
+static const struct vop_intr rk3328_vop_intr = {
+       .intrs = rk3368_vop_intrs,
+       .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
+       .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
+       .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
+       .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
+       .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
+       .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
+};
+
+static const struct vop_win_data rk3328_vop_win_data[] = {
+       { .base = 0xd0, .phy = &rk3288_win01_data,
+         .type = DRM_PLANE_TYPE_PRIMARY },
+       { .base = 0x1d0, .phy = &rk3288_win01_data,
+         .type = DRM_PLANE_TYPE_OVERLAY },
+       { .base = 0x2d0, .phy = &rk3288_win01_data,
+         .type = DRM_PLANE_TYPE_OVERLAY },
+       { .base = 0x3d0, .phy = &rk3288_win01_data,
+         .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_data rk3328_vop = {
+       .version = VOP_VERSION(3, 8),
+       .feature = VOP_FEATURE_OUTPUT_10BIT,
+       .max_input = {4096, 8192},
+       .max_output = {4096, 2160},
+       .intr = &rk3328_vop_intr,
+       .ctrl = &rk3328_ctrl_data,
+       .win = rk3328_vop_win_data,
+       .win_size = ARRAY_SIZE(rk3328_vop_win_data),
+};
+
 static const struct vop_scl_regs rk3066_win_scl = {
        .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
        .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
@@ -651,6 +728,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
          .data = &rk3399_vop_lit },
        { .compatible = "rockchip,rk322x-vop",
          .data = &rk322x_vop },
+       { .compatible = "rockchip,rk3328-vop",
+         .data = &rk3328_vop },
        {},
 };
 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index b9f986cfff75f6bba5685faf40d906f01b1e61bf..ad0bbd94fbd4ddae0f1890b37fc293578136f1fe 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -664,6 +664,175 @@
 #define RK3399_GAMMA_LUT_ADDR                  0x2000
 /* rk3399 register definition end */
 
+/* rk3328 register definition end */
+#define RK3328_REG_CFG_DONE                    0x00000000
+#define RK3328_VERSION_INFO                    0x00000004
+#define RK3328_SYS_CTRL                                0x00000008
+#define RK3328_SYS_CTRL1                       0x0000000c
+#define RK3328_DSP_CTRL0                       0x00000010
+#define RK3328_DSP_CTRL1                       0x00000014
+#define RK3328_DSP_BG                          0x00000018
+#define RK3328_AUTO_GATING_EN                  0x0000003c
+#define RK3328_LINE_FLAG                       0x00000040
+#define RK3328_VOP_STATUS                      0x00000044
+#define RK3328_BLANKING_VALUE                  0x00000048
+#define RK3328_WIN0_DSP_BG                     0x00000050
+#define RK3328_WIN1_DSP_BG                     0x00000054
+#define RK3328_DBG_PERF_LATENCY_CTRL0          0x000000c0
+#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0    0x000000c4
+#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0    0x000000c8
+#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0   0x000000cc
+#define RK3328_INTR_EN0                                0x000000e0
+#define RK3328_INTR_CLEAR0                     0x000000e4
+#define RK3328_INTR_STATUS0                    0x000000e8
+#define RK3328_INTR_RAW_STATUS0                        0x000000ec
+#define RK3328_INTR_EN1                                0x000000f0
+#define RK3328_INTR_CLEAR1                     0x000000f4
+#define RK3328_INTR_STATUS1                    0x000000f8
+#define RK3328_INTR_RAW_STATUS1                        0x000000fc
+#define RK3328_WIN0_CTRL0                      0x00000100
+#define RK3328_WIN0_CTRL1                      0x00000104
+#define RK3328_WIN0_COLOR_KEY                  0x00000108
+#define RK3328_WIN0_VIR                                0x0000010c
+#define RK3328_WIN0_YRGB_MST                   0x00000110
+#define RK3328_WIN0_CBR_MST                    0x00000114
+#define RK3328_WIN0_ACT_INFO                   0x00000118
+#define RK3328_WIN0_DSP_INFO                   0x0000011c
+#define RK3328_WIN0_DSP_ST                     0x00000120
+#define RK3328_WIN0_SCL_FACTOR_YRGB            0x00000124
+#define RK3328_WIN0_SCL_FACTOR_CBR             0x00000128
+#define RK3328_WIN0_SCL_OFFSET                 0x0000012c
+#define RK3328_WIN0_SRC_ALPHA_CTRL             0x00000130
+#define RK3328_WIN0_DST_ALPHA_CTRL             0x00000134
+#define RK3328_WIN0_FADING_CTRL                        0x00000138
+#define RK3328_WIN0_CTRL2                      0x0000013c
+#define RK3328_DBG_WIN0_REG0                   0x000001f0
+#define RK3328_DBG_WIN0_REG1                   0x000001f4
+#define RK3328_DBG_WIN0_REG2                   0x000001f8
+#define RK3328_DBG_WIN0_RESERVED               0x000001fc
+#define RK3328_WIN1_CTRL0                      0x00000200
+#define RK3328_WIN1_CTRL1                      0x00000204
+#define RK3328_WIN1_COLOR_KEY                  0x00000208
+#define RK3328_WIN1_VIR                                0x0000020c
+#define RK3328_WIN1_YRGB_MST                   0x00000210
+#define RK3328_WIN1_CBR_MST                    0x00000214
+#define RK3328_WIN1_ACT_INFO                   0x00000218
+#define RK3328_WIN1_DSP_INFO                   0x0000021c
+#define RK3328_WIN1_DSP_ST                     0x00000220
+#define RK3328_WIN1_SCL_FACTOR_YRGB            0x00000224
+#define RK3328_WIN1_SCL_FACTOR_CBR             0x00000228
+#define RK3328_WIN1_SCL_OFFSET                 0x0000022c
+#define RK3328_WIN1_SRC_ALPHA_CTRL             0x00000230
+#define RK3328_WIN1_DST_ALPHA_CTRL             0x00000234
+#define RK3328_WIN1_FADING_CTRL                        0x00000238
+#define RK3328_WIN1_CTRL2                      0x0000023c
+#define RK3328_DBG_WIN1_REG0                   0x000002f0
+#define RK3328_DBG_WIN1_REG1                   0x000002f4
+#define RK3328_DBG_WIN1_REG2                   0x000002f8
+#define RK3328_DBG_WIN1_RESERVED               0x000002fc
+#define RK3328_WIN2_CTRL0                      0x00000300
+#define RK3328_WIN2_CTRL1                      0x00000304
+#define RK3328_WIN2_COLOR_KEY                  0x00000308
+#define RK3328_WIN2_VIR                                0x0000030c
+#define RK3328_WIN2_YRGB_MST                   0x00000310
+#define RK3328_WIN2_CBR_MST                    0x00000314
+#define RK3328_WIN2_ACT_INFO                   0x00000318
+#define RK3328_WIN2_DSP_INFO                   0x0000031c
+#define RK3328_WIN2_DSP_ST                     0x00000320
+#define RK3328_WIN2_SCL_FACTOR_YRGB            0x00000324
+#define RK3328_WIN2_SCL_FACTOR_CBR             0x00000328
+#define RK3328_WIN2_SCL_OFFSET                 0x0000032c
+#define RK3328_WIN2_SRC_ALPHA_CTRL             0x00000330
+#define RK3328_WIN2_DST_ALPHA_CTRL             0x00000334
+#define RK3328_WIN2_FADING_CTRL                        0x00000338
+#define RK3328_WIN2_CTRL2                      0x0000033c
+#define RK3328_DBG_WIN2_REG0                   0x000003f0
+#define RK3328_DBG_WIN2_REG1                   0x000003f4
+#define RK3328_DBG_WIN2_REG2                   0x000003f8
+#define RK3328_DBG_WIN2_RESERVED               0x000003fc
+#define RK3328_WIN3_CTRL0                      0x00000400
+#define RK3328_WIN3_CTRL1                      0x00000404
+#define RK3328_WIN3_COLOR_KEY                  0x00000408
+#define RK3328_WIN3_VIR                                0x0000040c
+#define RK3328_WIN3_YRGB_MST                   0x00000410
+#define RK3328_WIN3_CBR_MST                    0x00000414
+#define RK3328_WIN3_ACT_INFO                   0x00000418
+#define RK3328_WIN3_DSP_INFO                   0x0000041c
+#define RK3328_WIN3_DSP_ST                     0x00000420
+#define RK3328_WIN3_SCL_FACTOR_YRGB            0x00000424
+#define RK3328_WIN3_SCL_FACTOR_CBR             0x00000428
+#define RK3328_WIN3_SCL_OFFSET                 0x0000042c
+#define RK3328_WIN3_SRC_ALPHA_CTRL             0x00000430
+#define RK3328_WIN3_DST_ALPHA_CTRL             0x00000434
+#define RK3328_WIN3_FADING_CTRL                        0x00000438
+#define RK3328_WIN3_CTRL2                      0x0000043c
+#define RK3328_DBG_WIN3_REG0                   0x000004f0
+#define RK3328_DBG_WIN3_REG1                   0x000004f4
+#define RK3328_DBG_WIN3_REG2                   0x000004f8
+#define RK3328_DBG_WIN3_RESERVED               0x000004fc
+
+#define RK3328_HWC_CTRL0                       0x00000500
+#define RK3328_HWC_CTRL1                       0x00000504
+#define RK3328_HWC_MST                         0x00000508
+#define RK3328_HWC_DSP_ST                      0x0000050c
+#define RK3328_HWC_SRC_ALPHA_CTRL              0x00000510
+#define RK3328_HWC_DST_ALPHA_CTRL              0x00000514
+#define RK3328_HWC_FADING_CTRL                 0x00000518
+#define RK3328_HWC_RESERVED1                   0x0000051c
+#define RK3328_POST_DSP_HACT_INFO              0x00000600
+#define RK3328_POST_DSP_VACT_INFO              0x00000604
+#define RK3328_POST_SCL_FACTOR_YRGB            0x00000608
+#define RK3328_POST_RESERVED                   0x0000060c
+#define RK3328_POST_SCL_CTRL                   0x00000610
+#define RK3328_POST_DSP_VACT_INFO_F1           0x00000614
+#define RK3328_DSP_HTOTAL_HS_END               0x00000618
+#define RK3328_DSP_HACT_ST_END                 0x0000061c
+#define RK3328_DSP_VTOTAL_VS_END               0x00000620
+#define RK3328_DSP_VACT_ST_END                 0x00000624
+#define RK3328_DSP_VS_ST_END_F1                        0x00000628
+#define RK3328_DSP_VACT_ST_END_F1              0x0000062c
+#define RK3328_BCSH_COLOR_BAR                  0x00000640
+#define RK3328_BCSH_BCS                                0x00000644
+#define RK3328_BCSH_H                          0x00000648
+#define RK3328_BCSH_CTRL                       0x0000064c
+#define RK3328_FRC_LOWER01_0                   0x00000678
+#define RK3328_FRC_LOWER01_1                   0x0000067c
+#define RK3328_FRC_LOWER10_0                   0x00000680
+#define RK3328_FRC_LOWER10_1                   0x00000684
+#define RK3328_FRC_LOWER11_0                   0x00000688
+#define RK3328_FRC_LOWER11_1                   0x0000068c
+#define RK3328_DBG_POST_REG0                   0x000006e8
+#define RK3328_DBG_POST_RESERVED               0x000006ec
+#define RK3328_DBG_DATAO                       0x000006f0
+#define RK3328_DBG_DATAO_2                     0x000006f4
+
+/* sdr to hdr */
+#define RK3328_SDR2HDR_CTRL                    0x00000700
+#define RK3328_EOTF_OETF_Y0                    0x00000704
+#define RK3328_RESERVED0001                    0x00000708
+#define RK3328_RESERVED0002                    0x0000070c
+#define RK3328_EOTF_OETF_Y1                    0x00000710
+#define RK3328_EOTF_OETF_Y64                   0x0000080c
+#define RK3328_OETF_DX_DXPOW1                  0x00000810
+#define RK3328_OETF_DX_DXPOW64                 0x0000090c
+#define RK3328_OETF_XN1                                0x00000910
+#define RK3328_OETF_XN63                       0x00000a08
+
+/* hdr to sdr */
+#define RK3328_HDR2SDR_CTRL                    0x00000a10
+#define RK3328_HDR2SDR_SRC_RANGE               0x00000a14
+#define RK3328_HDR2SDR_NORMFACEETF             0x00000a18
+#define RK3328_RESERVED0003                    0x00000a1c
+#define RK3328_HDR2SDR_DST_RANGE               0x00000a20
+#define RK3328_HDR2SDR_NORMFACCGAMMA           0x00000a24
+#define RK3328_EETF_OETF_Y0                    0x00000a28
+#define RK3328_SAT_Y0                          0x00000a2c
+#define RK3328_EETF_OETF_Y1                    0x00000a30
+#define RK3328_SAT_Y1                          0x00000ab0
+#define RK3328_SAT_Y8                          0x00000acc
+
+#define RK3328_HWC_LUT_ADDR                    0x00000c00
+
 /* rk3036 register definition */
 #define RK3036_SYS_CTRL                        0x00
 #define RK3036_DSP_CTRL0               0x04