phy: rockchip-inno-usb2: amend sm work to support legacy SoC

This adds amend logic of sm work to compatibly support some legacy SoCs,
because _host_utmi_linestate_ and _host_utmi_hostdisconnect_ GRF status
bits which are required for host sm work were not introduced in these
SoCs.

Change-Id: Ib4f499f592618930ac5016a63b7a530674aa6005
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

clk: rockchip: rk3368: add 216M and 126M for armclkb and armclkl

support 216M/126M for armclkb and armclkl

Change-Id: I047ac24ad5a176923a55bd6934f06afcf272660d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM64: dts: rk3368: add vop display node

Change-Id: Ie747e90413fbfabe95e9d3c2ae55e02eff2e4708
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

phy: rockchip-inno-usb2: don't power on otg phy in ls irq handler

The commit c590056b6ab8 ("phy: rockchip-inno-usb2: usb remote
wakeup support") power on otg phy in linestate irq handler,
this will cause usb peripheral fail to connect to PC in the
following case:
1. enable otg linestate irq
2. set system enter deep sleep
3. wakeup system by power key
4. connect usb peripheral to PC, pull up D+ to ~3V, trigger
   linestate irq and power on otg phy.
5. usb peripheral do BC1.2 detect, but PC try to enumerate
   the usb peripheral at the same time and fail at last.

Actually the usb controller drivers (e.g. dwc3 driver)
and otg_sm_work can manage the otg phy power consumption, so
it doesn't need to power on otg phy in linestate irq handler.

Change-Id: Ifd78e4d44ab96f07f75f063ed20af153b4027028
Signed-off-by: William Wu <wulf@rock-chips.com>

arm64: dts: rockchip: rk3368-p9: add ramp-delay for syr82x dcdc

Change-Id: I0a1cca68d6e40a881e153f824ccbeb611d006ff0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

usb: dwc_otg_310: pcd: fix isoc in ep transfer issue

When test usb gadget uvc function, we find a isoc in
ep transfer bug that will cause uvc data transfer fail.
The error case is:

1. The current EP request is done, call complete_ep()
to completes the request, and then call start_next_request()
to check the EP request queue, in this error case, the
queue is empty, so it doesn't start next request, just
set ep frame_num to 0xFFFFFFFF.

2. NAK Interrutp is triggered, check isoc ep frame_num
is 0xFFFFFFFF, then reset the frame_num to 0, and then
call start_next_request() to check the EP request queue,
in this error case, the queue is still empty, so set ep
frame_num to 0xFFFFFFFF again.

But afer the above operation, the current code will
modify the ep frame_num in NAK Interrutp handler by
add ep bInterval to frame_num, this cause frame_num
change again, but not keep in 0xFFFFFFFF, so the next
NAK Interrutp handler doesn't start next request any
more.

This patch reset the frame_num to the current frame
number got from DSTS SOFFN register if detect the
frame_num is 0xFFFFFFFF in NAK Interrutp handler.
And modify the frame_num in NAK Interrutp handler
only when the frame_num is not 0xFFFFFFFF.

TEST=Set usb gadget as webcam, use Ubuntu Guvcview
to preview the webcam, observe the preview screen
and the error log "There are no more ISOC requests".

Change-Id: I4403a67b1d5d257d092a2a71d5666c5d6fd5af3c
Signed-off-by: William Wu <wulf@rock-chips.com>

clk: rockchip: rk3368 add 1296000 support to freq table

Change-Id: I6cff0d8820401c36c98f54a9777629dc1d37fba8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Revert "Revert "MALI: midgard: support sharing regulator with other devices""

This reverts commit eb6c2ed7207f4dd086548dd58589ed4ea042504f.

Change-Id: I09424d08bfac3457da24b10fe2b97d2856399e63
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

Revert "Revert "MALI: midgard: avoid GPU voltage domain keeping the initial voltage""

This reverts commit e7db50b51268386fd0e9f88a95c45a4ef3454c4e.

Change-Id: I47f9c1d114b06264d6dd4098bc0e00228fd8f187
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: midgard: RK: add wake_lock for delayed_work_to_power_off_gpu

To ensure that the work is executed before system being suspended.

Change-Id: Iec1bd114dfff53e2464540f09ced66cf6be81d1a
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

net: wireless: rockchip: fix compile error for rtl8822be

Fixes: 4d99f97 ("net: wireless: rockchip: add rtl8822be ...")
Change-Id: I40234ce807ef9289f422e762e2c94e163fe1824d
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

ARM64: dts: rk3368: add rk3368-p9.dts for p9 board

Change-Id: Id7e718b4f670aa91768db695e5c38da88f048987
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3368-android enable usb otg

Change-Id: Idd9e683c1c48dad940779dbb701dd4271ca8292f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

net: wireless: rockchip: disable build rtl8822be pcie wifi by default

Until fix this compile error:
ERROR: "Array_MP_8822B_FW_NIC" [drivers/net/wireless/rockchip_wlan/rtl8822be/8822be.ko] undefined!

Change-Id: I78afda57761bb0bd7737864e5d04deeaa1b7df8a
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rk3368: add rk3368-sheep.dts for sheep board

rework for rk3368-tb.dtsi and rk3368-tb-sheep.dts, intergrate them
to rk3368-sheep.dts

Change-Id: Ieb9198be7c80a5c8c31b0a1990bac22079548eea
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3368: Add iommu node for ISP/HEVC/VOP/VPU

Change-Id: I8193fa6f4cf186c2122b56d652f076024f517fb7
Signed-off-by: Simon <xxm@rock-chips.com>

arm64: dts: rockchip: add cpu-avs device node for rk3368

Add cpu-avs node in the device tree for the ARM64 rk3368 SoC.

Change-Id: Ie7eee09c20b06bd755b9277e0acd8eaf810c5331
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rockchip: add efuse device node for rk3368

Add a efuse node in the device tree for the ARM64 rk3368 SoC.

Change-Id: I7d13febf73e336d5b9d1046ffe6ed69d99ea9dd6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

nvmem: rockchip-efuse: add rk3368-efuse support

This adds the necessary data for handling efuse on the rk3368.
As efuse of rk3368 is secure, use secure interface to access efuse.

Change-Id: I72c29348b7744b232d75ab51c56dc7de0988c24e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: use rk3368-efuse clock ids

Reference the newly added efuse clock-ids in the clock-tree.

Change-Id: Ibbef52bcc44d006ab48e6f1f874e3bc88c681bd6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: add ids for efuse pclk on rk3368

Adds new ids for the pclk supplying the efuse on rk3368 socs.

Change-Id: I69f0daf402d62079e47d8df8f6e9bef0b274239f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

firmware: rockchip: sip: add secure register read/write

Change-Id: If1369fb63a2618d20bfe7edffdc49bd4a959f954
Signed-off-by: chenjh <chenjh@rock-chips.com>

clk: rockchip: fix up the rockchip_rk3066_pll_clk_set_by_auto func

Change-Id: Id7c561a50a16918c2943f79701ab72c6eaccdc41
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

drm/rockchip: rga: fix potential buffer overflow

Change-Id: Id923e38264855320fbe994bed156bf16eac60245
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

drm/rockchip: rga: don't flush buffer context

to save time

Change-Id: Ie4a1618eabdbb9ebf5ad0b73b8acc9df884a81bb
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

ARM: dts: rk3288: add dma-coherent to rga

RGA are used for scale copy buffer form vpu,isp,
no need to flush CPU cache

Change-Id: Id3cfa0560a14cea122321dc1ea814aa8ec5dd4b6
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

driver, touch, gt9xx: enable regulator default

Change-Id: I6e3e7fe6102c83058078486104f88a31cdf1d65b
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: configs: rockchip_defconfig: enable mailbox and scpi

This adds select mailbox and scpi support.

Change-Id: I98fa6ee1ca210779b44c1351b68e8725071de07a
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

arm64: dts: rockchip: enable mbox related for rk3368-tb

This adds enable mbox and scpi function for rk3368-tb board.

Change-Id: I0b4866b72ad59892bc1c051c60bafd1a15ddce14
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

arm64: dts: rockchip: add mbox related nodes for rk3368

This adds support rk3368-mbox and scpi nodes for rk3368 SoC.

Change-Id: Ifdb90f8101c67ec579b5bba28f163527ed096c4c
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

mailbox: rk3368: add mailbox and scpi function

Add mailbox and scpi protocol function support for rk3368 SoC.

Change-Id: I201c916865eb2729ed135c3f5a77a9dd97007952
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

video: rockchip: vcodec: fix the output buffer of jpeg

The JPEG decoder is also able to output the raw image in
NV12 format without the help of Post Processor of decoder
in VDPU1.

Change-Id: I1b29a5d93d2dd8ae2f21a7537cc3493adf57d022
Signed-off-by: Randy Li <randy.li@rock-chips.com>

soc: rockchip: add virtual poweroff support

Change-Id: I79240fa936eee3e64eb74eb5d5cdc952c3b2ac9b
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

ARM64: dts: rk3399: config rockchip_suspend

Change-Id: I41e7e77b1cc903200c7e1711bae15c629a616564
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

ARM64: dts: rk3399-mid-818: enable hdmi on vopl

Change-Id: Ic42cd1895aaf0326671a30b4971c79b8ab309b4e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: rockchip_defconfig: enable CONFIG_FW_LOADER_USER_HELPER_FALLBACK

Change-Id: Ide84478567d97b53359619bd646c3d11c89e2485
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

arm64: dts: rockchip: rk3328: Fix the saradc compitiable

The rk3328 saradc is the same as rk3399, so change the compitiable,
they are both 6 channels.

Change-Id: Ia6104e8c5c3590cc745792b8cd3a457a15bb53d2
Signed-off-by: David Wu <david.wu@rock-chips.com>

arm64: dts: rockchip: rk3328: remove the gmac m0 pins

The RK3328 datasheet is not define the pins of gmac m0,
so remove them.

Change-Id: Ic537586c76bd2f3a937c1e15b5877744598cc702
Signed-off-by: David Wu <david.wu@rock-chips.com>

arm64: dts: rockchip: rk3328: Use new define for RK3328 pins

Change-Id: I33ba7d3ae0fd93e94fe661936d90f2100f478205
Signed-off-by: David Wu <david.wu@rock-chips.com>

include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl

Add gpio pin index definition to make it easier to describe
GPIO in dts.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I4aa6c01f96d91fd8ddcb371fd01ca9629f1a3013

net: wireless: rockchip_wlan: update for ap6xxx wifi firmware

bcmdhd driver support ko module or compile into kernel

Change-Id: I260c9d3c3da0a9e249a4ee3883ed3efe03964ddf
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

linux: mfd: rk808: fix up the RK818_NUM_REGULATORS

Change-Id: I049286ec7afcaa66ca88458f51a3e0d516121001
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

FROMLIST: drm/bridge: analogix_dp: Don't read EDID if panel present

If there's a panel connected to the analogix_dp bridge, rely on
the panel driver for modes, rather than reading EDID *and* calling
get_modes() on the panel.

This allows panels with a valid EDID to read it in the panel driver
(e.g. simple_panel), and panels with invalid EDID to homebrew modes
in their get_modes implementation.

BUG=chrome-os-partner:53565
TEST=Boot device and confirm the modes returned are from panel driver
     instead of EDID

[from https://patchwork.freedesktop.org/patch/107115/]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374959
Commit-Ready: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Change-Id: Ie07dd33e3c121215bf24394cfcb3fff8c7c746a5
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: rockchip_defconfig: enable CONFIG_BT_RTKBTUSB

Change-Id: I571f3c53cb63a0f5f4d11c2e3dd128d828815b47
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

net: wireless: rockchip: add rtl8822be pcie wifi driver

Change-Id: Ibdc9a9272bf5221b56e2c63b59ffcba41674994c
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

arm64: rockchip_defconfig: enable CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP

Change-Id: Idd64d6b137dc4bdabfd553bd6912d75a405b6485
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

iommu/rockchip: don't do power domain enable on probe

Change-Id: I1484cbe6f7aa4fe358a3223de62a19aabee29d5c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3368-android: assigned aclk_vop to 400Mhz

Change-Id: Ie70934cb7046aa96a94e14b251d11e87a98b1512
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3368-android: set firmware_class.path=/system/vendor/firmware

It's required by gpu driver, which will load firmware through
/system/vendor/firmware.

If android finds another way to fix it, then can be reverted.

Change-Id: I2fede28f022f10c2e16f68b21159a638a10a53ec
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

staging: ion: add api to set/get platform device

Change-Id: Ic251497b173608e1f98bf68fbf2b54b75f89c143
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Revert "arm64/dma-mapping: __generic_dma_ops always call swiotlb_dma_ops"

This reverts commit 3e89f7de9a3abe9cff127e161d4e11699554cb76.

Change-Id: I4cf45807f91ab3021b6593f171c1f2573e1ea7f2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3399 box: enable hdmi_dp_sound

Change-Id: I04bdec75510b3e47a62a5093fdbd6ec66926e282
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: dts: rk3399-android: add hdmi-dp drm audio

this patch register hdmi and dp as one sound card, and compatible
single hdmi audio, single dp audio or both.

Change-Id: I840e6c13f1a0c765a3a9235eb0a798011fc3bf06
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: configs: rockchip: enable SND_SOC_ROCKCHIP_HDMI_DP

Change-Id: Icce0802191f2f92913ffc637c50d849bfa79859a
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm/rockchip: cdn-dp: return zero when dp is inactive

Change-Id: I741b8ac140014c7f046f59e371ed3ddb245468a2
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: rockchip: add machine driver for built-in hdmi and dp

this patch is used for rockchip built-in HDMI and DP audio output which are
wired to the same i2s line. so we use a DAI link CPU to multicodecs.

Change-Id: Ie8d1ede201a4d4b4cd11c8c05cd1f6177d844957
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

UPSTREAM: ASoC: soc-core: snd_soc_get_dai_name() become non static

snd_soc_get_dai_name() is used from snd_soc_of_get_dai_name(),
and it is assuming that DT is using "sound-dai" / "#sound-dai-cells".
But graph base DT is using "remote-endpoint". This patch makes
snd_soc_get_dai_name() non static for graph support.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 1ad8ec535b997ed36c0f32c2616206725258dd30)

Change-Id: If99dcbfa722f09e3238cfafb5dc2803b6636a2e0

arm64: dts: rockchip: amend usb-otg related nodes for rk3368-tb

This adds move some common properties of usb-otg from dts to dtsi.

Change-Id: I84355433b5ca63cc0b763d66dcdbb38897635418
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM: dts: rockchip: use hdmi-ddc for ddc bus in rk3288

Using the builtin I2C controller in dw_hdmi is better than using the
normal RK3288 I2C controller(I2C5).

Test: work normally when switch mode between 4K@60hz|4K@30hz|1080P..
Change-Id: Ifb4b72ca5649efb0cc3055f2db34ebbcc2377c4c
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

arm64: dts: rockchip: use hdmi-ddc for ddc bus in rk3399

Using the builtin I2C controller in dw_hdmi is better than using the
normal RK3399 I2C controller(I2C3).

Change-Id: I6a2de7221263e8564f7cca56ea5c52e1a133c138
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

FROMLIST: drm/bridge: dw_hdmi: support i2c extended read mode

"I2C Master Interface Extended Read Mode" implements a segment
pointer-based read operation using the Special Register configuration.

This patch fix https://patchwork.kernel.org/patch/7098101/ mentioned
"The current implementation does not support "I2C Master Interface
Extended Read Mode" to read data addressed by non-zero segment
pointer, this means that if EDID has more than 1 extension blocks"

With this patch,dw-hdmi can read EDID data with 1/2/4 blocks.

(am from https://patchwork.kernel.org/patch/9586343/)

BUG=chrome-os-partner:59768
TEST=fievel can read 1/2/4 blocks EDID data

Change-Id: I086e6ea63ec69c0532be445b958ce253a7f1f3cc
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/442308
Reviewed-by: Douglas Anderson <dianders@chromium.org>

video: rockchip: vop: add ourput color bt601, bt709, bt2020

Change-Id: I0b679244817f1a524d6f834ade32dce1666a6352
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
(cherry picked from commit b76f11e6652a825fd4cb7798ec3fe06c60587338)

arm64: dts: rk3399: sapphire-excavator: enabled hdmi sound

Change-Id: If95f0b885aa3afdbaa985b4b39628502075be90e
Signed-off-by: wlq <wlq@rock-chips.com>

clk: rockchip: rk3368: add CLK_IGNORE_UNUSED flag for mcu clk

Change-Id: I27856c9523ac3bffd4b509f016a659a1e3094b41
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: pwm: Use pwm_get/set_xxx() helpers where appropriate

Use pwm_get/set_xxx() helpers instead of directly accessing the pwm->xxx
field. Doing that will ease adaptation of the PWM framework to support
atomic update.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 4b58896f72176b781816a9e14dcea5f755b19b5c)

Change-Id: Ic6bdaf2017bb292ef920604fba86805999cebf0c
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: dts: rockchip: sync pmugrf with upstream for rk3399

Change-Id: I0b023824265418c72413e6702fbc5592eba0dc4e
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: dts: rockchip: rename ethernet node name for rk3399

Same as upstream.

Change-Id: I737f7974d01a22abc697483956db795e7e151fe0
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

UPSTREAM: arm64: dts: rockchip: add rk3399 thermal_zones phandle

We're going to need to amend this table in board files.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 647cea2e68420fa73efb97c908cdf0c852c22cec)

Change-Id: Ife7affa44554622b1b35ad6756cef78d22c69a3a
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: dts: rockchip: reorder some nodes for rk3399

keep order as upstream.

Change-Id: I52e0dfe97f0d12c550603675085a66346529794d
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rockchip: rk3399: change the pll init freq

set npll init freq 600M
set gpll init freq 800M

Change-Id: I110cc4b4051504dd875712bce9e473f74d8578b4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

pwm: rockchip: Fix the warning for rockchip_linux_defconfig

This patch fix the following warning:
drivers/pwm/pwm-rockchip.c:176:6: warning: unused variable 'ret' [-Wunused-variable]

Change-Id: I9ac08ad08fdefee5b875d36592936b07f032586c
Signed-off-by: David Wu <david.wu@rock-chips.com>

net: wireless: rockchip_wlan: update realtek wifi support

support wifi driver work as ko module or compile into kernel

1. wifi driver work as ko module, configs show as below:

CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP=n
CONFIG_RTL8188EU = m and CONFIG_RTL8188FU = m

2. wifi driver compile into kernel, configs show as below:
ps: Only one Realtek driver can be compiled into the kernel
CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP=y
CONFIG_RTL8188EU = y or CONFIG_RTL8188FU = y

Change-Id: I40e33a6f27597f9f90d9987d189b74fb637c40c1
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

arm64: dts: rockchip: rk3399: set ir irq handle on cpu1

Change-Id: I89f75184af810a050f6ca09daeba17774af4465e
Signed-off-by: Huang zhibao <hzb@rock-chips.com>

drm/rockchip: vop: fix background color on yuv domain

On yuv domain, background need use 10bit yuv format.

Change-Id: I02fe3894ac12b509e22c0d90977bcb7e4535c16d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: dw_hdmi: support ROCKCHIP_OUT_MODE_YUV420

VOP output mode and bus_format must be ROCKCHIP_OUT_MODE_YUV420
and MEDIA_BUS_FMT_YUV8_1X24 when display mode has a YCbCr420
flag.

Change-Id: Ib2d51c119f5a8f1b8a9285c47ab228b22a293d56
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm: bridge/dw_hdmi: support HDMI 2.0 YCbCr 4:2:0

Change-Id: I21fe667e8beeaf2f9b46fce043b6e14b366a3e05
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rockchip: rk3368: add ramp-delay for syr82x dcdc

Change-Id: I61ef71b32aa708123909124b89f61e8a8f3a1bb7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

mfd: rk818: use rk808-regulator

Change-Id: Ib7150f229a4682b6d0f4c5a6776a9ebc8565d221
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

drm: redefine YCbCr420 flag to bits 23:24

Since bits[19:22] have been used for picture aspect ratio
in upstream patch 876f43c073d79ad3f14a4cebd1aea1f39fc4daf5.
We define YCbCr420 flag to the subsequent bits.

Change-Id: I2eff8b51227fc7beb4f587e90bc070ae865ba9d4
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

UPSTREAM: drm: add picture aspect ratio flags

This patch adds drm flag bits for aspect ratio information

Currently drm flag bits don't have field for mode's picture
aspect ratio. This field will help the driver to pick mode with
right aspect ratio, and help in setting right VIC field in avi
infoframes.

V2: Addressed review comments from Sean
- Changed PAR-> PIC_AR
V3: Rebase
V3: Added r-b by Jose

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
Reviewed-by: Jose Abreu <Jose.Abreu@synopsys.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1476705880-15600-2-git-send-email-shashank.sharma@intel.com
(cherry picked from commit 876f43c073d79ad3f14a4cebd1aea1f39fc4daf5)
Change-Id: I7dc4d82722d4824ba2b6c041080373175b8f6d18
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm/rockchip: gem: reorder pages if page chunk less than 8

Change-Id: I03a91d2f9c017086b3cb35edeaf6b7913b147b9b
Signed-off-by: Simon <xxm@rock-chips.com>

ARM64: dts: rk3399: Add pd/clk for iommu

Change-Id: I6da7372e82a031140fead601a0661260be75855b
Signed-off-by: Simon <xxm@rock-chips.com>

drm/rockchip: support YUV420 output mode

Change-Id: I7b991c544df6da81be93d84febe59fc5089895ca
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: fixup color space table

Change-Id: Ia3c14602ffe837efd2fb4dcf8d3dd2c0960cfce6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

video: rockchip: vcodec: add reg_rlc inside dec_pp

dec_pp also need to remap input fd.

Change-Id: Ic19a14a5ccc002b5be36d90ec3114244d5e494aa
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

ARM64: dts: rockchip: rk3399: invert the pwm polarity

invert the pwm polarity for new pwm interface

Change-Id: I8dfde14fbc4fd4aa907722f260ce72fdb4d7d3bb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

video: backlight: pwm_bl: Fix the bug of Splashing screen when boot

The pwm_apply_args() should be removed when switching to the atomic
PWM API. Oherwise, the screen would splashing as the backlight is
disabled once when boot.

Change-Id: I0cadd471db54140192c39b9d7c6a673862e8f8d8
Signed-off-by: David Wu <david.wu@rock-chips.com>

pwm: rockchip: State of pwm clock should synchronize with pwm enabled state

If the pwm was not enabled at uboot loader, pwm could not work for clock
always disabled at pwm driver. The pwm clock is enabled at beginning of
pwm_apply(), but disabled at end of pwm_apply().

If the pwm was enabled at uboot loader, pwm clock is always enabled unless
closed by ATF. The pwm-backlight might turn off the power at early suspend,
should disable pwm clock for saving power consume.

It is important to provide opportunity to enable/disable clock at pwm driver,
the pwm consumer should ensure correct order to call pwm enable/disable, and
pwm driver ensure state of pwm clock synchronized with pwm enabled state.

Change-Id: I545db81eb638957567abacb93fd06fff9dd7181b
Fixes: 2bf1c98aa5a4 ("pwm: rockchip: Add support for atomic update")
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pwm: cros-ec: Add __packed to prevent padding

While the particular usage in question is likely safe (struct
cros_ec_command is 32-bit aligned, followed by <= 32-bit fields), it's
been suggested this is not a great pattern to follow for the general
case -- for example, if we follow a 'struct cros_ec_command' (which is
32-bit- but not 64-bit-aligned) with a struct that starts with a 64-bit
type (e.g., u64), the compiler may add padding.

Let's add __packed, to inform the compiler of our true intention -- to
have no padding between these struct elements -- and to future proof for
any refactorings that might occur.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 065cfbbb638cce3d388020c4b97813b4a904a7c3)

Change-Id: Iddd499863dde168679a88c2f9ecc461316b417a0
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pwm: Add ChromeOS EC PWM driver

Use the new ChromeOS EC EC_CMD_PWM_{GET,SET}_DUTY commands to control
one or more PWMs attached to the Embedded Controller. Because the EC
allows us to modify the duty cycle (as a percentage, where U16_MAX is
100%) but not the period, we assign the period a fixed value of
EC_PWM_MAX_DUTY and reject all attempts to change it.

This driver supports only device tree at the moment, because that
provides a very flexible way of describing the relationship between PWMs
and their consumer devices (e.g., backlight). On a non-DT system, we'll
probably want to use the non-GENERIC addressing (i.e., we'll need to
make special device instances that will use EC_PWM_TYPE_KB_LIGHT or
EC_PWM_TYPE_DISPLAY_LIGHT), as well as the relatively inflexible
pwm_lookup infrastructure for matching devices. Defer that work for now.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 1f0d3bb02785f698dc273b9006a473194c32f874)

Change-Id: I47dbb20b10ae1b941e50e9a783cb708dff8f7efd
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: dt-bindings: pwm: Add binding for ChromeOS EC PWM

The ChromeOS Embedded Controller can support controlling its attached
PWMs via its host-command interface. The number of supported PWMs varies
on a per-board basis, but we can autodetect this by checking the error
codes, so we don't need an extra property for this. And because the EC
only allows specifying the duty cycle and not the period, we don't
specify the period via pwm-cells, and instead have only support for one
cell -- to specify the index.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 9e60f50b4a79ae2df791d89d08cf2b78ad7629bd)

Change-Id: Ibb2ac5cff1e8cc2ab43c9f1f89e68e48da23d897
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: regulator: pwm: Document pwm-dutycycle-unit and pwm-dutycycle-range

Document the pwm-dutycycle-unit and pwm-dutycycle-range properties.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 58fd822b2e344edae6b4dbc09b19bd0c4a2f8f60)

Change-Id: I029307b54210f2203276a467e947d0fa2e51966d
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: regulator: pwm: Support extra continuous mode cases

The continuous mode allows one to declare a PWM regulator without having
to declare the voltage <-> dutycycle association table. It works fine as
long as your voltage(dutycycle) function is linear, but also has the
following constraints:

- dutycycle for min_uV = 0%
- dutycycle for max_uV = 100%
- dutycycle for min_uV < dutycycle for max_uV

While the linearity constraint is acceptable for now, we sometimes need to
restrict of the PWM range (to limit the maximum/minimum voltage for
example) or have a min_uV_dutycycle > max_uV_dutycycle (this could be
tweaked with PWM polarity, but not all PWMs support inverted polarity).

Add the pwm-dutycycle-range and pwm-dutycycle-unit DT properties to define
such constraints. If those properties are not defined, the PWM regulator
use the default pwm-dutycycle-range = <0 100> and
pwm-dutycycle-unit = <100> values (existing behavior).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit ea398e28739e25651ede7ddf5aeb57cbcbc8ca7d)

Change-Id: I6e10c93a6620113e1463221d461fc23ccf3fe398
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pwm: rockchip: Add support for atomic update

Implement the ->apply() function to add support for atomic update.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(commit 2bf1c98aa5a41651f5e6455117ff06f66ff3cc50)

Conflicts:
drivers/pwm/pwm-rockchip.c

Change-Id: I92745cf301c26d20da284da8234e244828598d52
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pwm: rockchip: Avoid glitches on already running PWMs

The current logic will disable the PWM clk even if the PWM was left
enabled by the bootloader (because it's controlling a critical device
like a regulator for example).
Keep the PWM clk enabled if the PWM is enabled to avoid any glitches.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(commit 48cf973cae33488f84d7ab79a0f613383cff4de4)

Conflicts:
drivers/pwm/pwm-rockchip.c

Change-Id: I75ffccd19c5244568fc0034d1585dac490296111
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pwm: rockchip: Add support for hardware readout

Implement the ->get_state() function to expose initial state.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 1ebb74cf3537135f157beddf1a4366070155edda)

Change-Id: Ia7454ce2f96ee814118724fa98bdd41d8b5ae922
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pwm: rockchip: Fix period and duty cycle approximation

The current implementation always round down the duty and period values,
while it would be better to round them to the closest integer.

These changes are needed in preparation of atomic update support to
prevent a period/duty cycle drift when executing several times the
'pwm_get_state() / modify / pwm_apply_state()' sequence.

Say you have an expected period of 3.333 us and a clk rate of
112.666667 MHz -- the clock frequency doesn't divide evenly, so the
period (stashed in nanoseconds) shrinks when we convert to the register
value and back, as follows:

  pwm_apply_state(): register = period * 112666667 / 1000000000;
  pwm_get_state(): period = register * 1000000000 / 112666667;

or in other words:

  period = period * 112666667 / 1000000000 * 1000000000 / 112666667;

which yields a sequence like:

  3333 -> 3328
  3328 -> 3319
  3319 -> 3310
  3310 -> 3301
  3301 -> 3292
  3292 -> ... (etc) ...

With this patch, we'd see instead:

  period = div_round_closest(period * 112666667, 1000000000) *
                   1000000000 / 112666667;

which yields a stable sequence:

  3333 -> 3337
  3337 -> 3337
  3337 -> ... (etc) ...

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 12f9ce4a519845070d338253ab9528b5d7e2df34)

Change-Id: Ife75404e663d1380725d634ac621b2ca9f831791
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: regulator: pwm: Retrieve correct voltage

The continuous PWM voltage regulator is caching the voltage value in
the ->volt_uV field. While most of the time this value should reflect the
real voltage, sometime it can be sightly different if the PWM device
rounded the set_duty_cycle request.
Moreover, this value is not valid until someone has modified the regulator
output.

Remove the ->volt_uV field and always rely on the PWM state to calculate
the regulator output.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit d9070fdbe40a04b61262bac0f7ff0c7c29a68015)

Change-Id: Iba7b143c1b08d547b5cd46ac42d9051fb34309df
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: regulator: pwm: Properly initialize the ->state field

The ->state field is currently initialized to 0, thus referencing the
voltage selector at index 0, which might not reflect the current
voltage value.
If possible, retrieve the current voltage selector from the PWM state,
else return -EINVAL.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 87248991a1de28e73dc30057e82d831bc11cdd44)

Change-Id: I179395dc7bad7aa867e68c92be7ce92b03ae7112
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: regulator: pwm: Switch to the atomic PWM API

Use the atomic API wherever appropriate and get rid of pwm_apply_args()
call (the reference period and polarity are now explicitly set when
calling pwm_apply_state()).

We also make use of the pwm_set_relative_duty_cycle() helper to ease
relative to absolute duty_cycle conversion.

Note that changes introduced by commit fd786fb0276a ("regulator: pwm:
Try to avoid voltage error in duty cycle calculation") are no longer
needed because pwm_set_relative_duty_cycle() takes care of all rounding
approximation for us.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 3f4eb39be9b1402ea01a5c67441d0b0bcb74b4b2)

Change-Id: Id12d4d625fb6e1e5ff3725737cc9232e4df40c36
Signed-off-by: David Wu <david.wu@rock-chips.com>