drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28
  29 #include "rockchip_drm_drv.h"
  30 #include "rockchip_drm_vop.h"
  31
  32 #define DRIVER_NAME    "dw-mipi-dsi"
  33
  34 #define RK3288_GRF_SOC_CON6             0x025c
  35 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  36 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  37
  38 #define RK3399_GRF_SOC_CON19            0x6250
  39 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  40 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  41
  42 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  43 #define RK3399_GRF_SOC_CON22            0x6258
  44 #define RK3399_GRF_DSI_MODE             0xffff0000
  45
  46 #define DSI_VERSION                     0x00
  47 #define DSI_PWR_UP                      0x04
  48 #define RESET                           0
  49 #define POWERUP                         BIT(0)
  50
  51 #define DSI_CLKMGR_CFG                  0x08
  52 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  53 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  54
  55 #define DSI_DPI_VCID                    0x0c
  56 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  57
  58 #define DSI_DPI_COLOR_CODING            0x10
  59 #define EN18_LOOSELY                    BIT(8)
  60 #define DPI_COLOR_CODING_16BIT_1        0x0
  61 #define DPI_COLOR_CODING_16BIT_2        0x1
  62 #define DPI_COLOR_CODING_16BIT_3        0x2
  63 #define DPI_COLOR_CODING_18BIT_1        0x3
  64 #define DPI_COLOR_CODING_18BIT_2        0x4
  65 #define DPI_COLOR_CODING_24BIT          0x5
  66
  67 #define DSI_DPI_CFG_POL                 0x14
  68 #define COLORM_ACTIVE_LOW               BIT(4)
  69 #define SHUTD_ACTIVE_LOW                BIT(3)
  70 #define HSYNC_ACTIVE_LOW                BIT(2)
  71 #define VSYNC_ACTIVE_LOW                BIT(1)
  72 #define DATAEN_ACTIVE_LOW               BIT(0)
  73
  74 #define DSI_DPI_LP_CMD_TIM              0x18
  75 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  76 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  77
  78 #define DSI_DBI_CFG                     0x20
  79 #define DSI_DBI_CMDSIZE                 0x28
  80
  81 #define DSI_PCKHDL_CFG                  0x2c
  82 #define EN_CRC_RX                       BIT(4)
  83 #define EN_ECC_RX                       BIT(3)
  84 #define EN_BTA                          BIT(2)
  85 #define EN_EOTP_RX                      BIT(1)
  86 #define EN_EOTP_TX                      BIT(0)
  87
  88 #define DSI_MODE_CFG                    0x34
  89 #define ENABLE_VIDEO_MODE               0
  90 #define ENABLE_CMD_MODE                 BIT(0)
  91
  92 #define DSI_VID_MODE_CFG                0x38
  93 #define FRAME_BTA_ACK                   BIT(14)
  94 #define ENABLE_LOW_POWER                (0x3f << 8)
  95 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  96 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
  97 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
  98 #define VID_MODE_TYPE_BURST             0x2
  99
 100 #define DSI_VID_PKT_SIZE                0x3c
 101 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 102 #define VID_PKT_MAX_SIZE                0x3fff
 103
 104 #define DSI_VID_NUM_CHUMKS              0x40
 105 #define DSI_VID_NULL_PKT_SIZE           0x44
 106 #define DSI_VID_HSA_TIME                0x48
 107 #define DSI_VID_HBP_TIME                0x4c
 108 #define DSI_VID_HLINE_TIME              0x50
 109 #define DSI_VID_VSA_LINES               0x54
 110 #define DSI_VID_VBP_LINES               0x58
 111 #define DSI_VID_VFP_LINES               0x5c
 112 #define DSI_VID_VACTIVE_LINES           0x60
 113 #define DSI_CMD_MODE_CFG                0x68
 114 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 115 #define DCS_LW_TX_LP                    BIT(19)
 116 #define DCS_SR_0P_TX_LP                 BIT(18)
 117 #define DCS_SW_1P_TX_LP                 BIT(17)
 118 #define DCS_SW_0P_TX_LP                 BIT(16)
 119 #define GEN_LW_TX_LP                    BIT(14)
 120 #define GEN_SR_2P_TX_LP                 BIT(13)
 121 #define GEN_SR_1P_TX_LP                 BIT(12)
 122 #define GEN_SR_0P_TX_LP                 BIT(11)
 123 #define GEN_SW_2P_TX_LP                 BIT(10)
 124 #define GEN_SW_1P_TX_LP                 BIT(9)
 125 #define GEN_SW_0P_TX_LP                 BIT(8)
 126 #define EN_ACK_RQST                     BIT(1)
 127 #define EN_TEAR_FX                      BIT(0)
 128
 129 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 130                                          DCS_LW_TX_LP | \
 131                                          DCS_SR_0P_TX_LP | \
 132                                          DCS_SW_1P_TX_LP | \
 133                                          DCS_SW_0P_TX_LP | \
 134                                          GEN_LW_TX_LP | \
 135                                          GEN_SR_2P_TX_LP | \
 136                                          GEN_SR_1P_TX_LP | \
 137                                          GEN_SR_0P_TX_LP | \
 138                                          GEN_SW_2P_TX_LP | \
 139                                          GEN_SW_1P_TX_LP | \
 140                                          GEN_SW_0P_TX_LP)
 141
 142 #define DSI_GEN_HDR                     0x6c
 143 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 144 #define GEN_HDATA_MASK                  (0xffff << 8)
 145 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 146 #define GEN_HTYPE_MASK                  0xff
 147
 148 #define DSI_GEN_PLD_DATA                0x70
 149
 150 #define DSI_CMD_PKT_STATUS              0x74
 151 #define GEN_CMD_EMPTY                   BIT(0)
 152 #define GEN_CMD_FULL                    BIT(1)
 153 #define GEN_PLD_W_EMPTY                 BIT(2)
 154 #define GEN_PLD_W_FULL                  BIT(3)
 155 #define GEN_PLD_R_EMPTY                 BIT(4)
 156 #define GEN_PLD_R_FULL                  BIT(5)
 157 #define GEN_RD_CMD_BUSY                 BIT(6)
 158
 159 #define DSI_TO_CNT_CFG                  0x78
 160 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 161 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 162
 163 #define DSI_BTA_TO_CNT                  0x8c
 164 #define DSI_LPCLK_CTRL                  0x94
 165 #define AUTO_CLKLANE_CTRL               BIT(1)
 166 #define PHY_TXREQUESTCLKHS              BIT(0)
 167
 168 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 169 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 170 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 171
 172 #define DSI_PHY_TMR_CFG                 0x9c
 173 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 174 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 175 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 176
 177 #define DSI_PHY_RSTZ                    0xa0
 178 #define PHY_DISFORCEPLL                 0
 179 #define PHY_ENFORCEPLL                  BIT(3)
 180 #define PHY_DISABLECLK                  0
 181 #define PHY_ENABLECLK                   BIT(2)
 182 #define PHY_RSTZ                        0
 183 #define PHY_UNRSTZ                      BIT(1)
 184 #define PHY_SHUTDOWNZ                   0
 185 #define PHY_UNSHUTDOWNZ                 BIT(0)
 186
 187 #define DSI_PHY_IF_CFG                  0xa4
 188 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 189 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 190
 191 #define DSI_PHY_STATUS                  0xb0
 192 #define LOCK                            BIT(0)
 193 #define STOP_STATE_CLK_LANE             BIT(2)
 194
 195 #define DSI_PHY_TST_CTRL0               0xb4
 196 #define PHY_TESTCLK                     BIT(1)
 197 #define PHY_UNTESTCLK                   0
 198 #define PHY_TESTCLR                     BIT(0)
 199 #define PHY_UNTESTCLR                   0
 200
 201 #define DSI_PHY_TST_CTRL1               0xb8
 202 #define PHY_TESTEN                      BIT(16)
 203 #define PHY_UNTESTEN                    0
 204 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 205 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 206
 207 #define DSI_INT_ST0                     0xbc
 208 #define DSI_INT_ST1                     0xc0
 209 #define DSI_INT_MSK0                    0xc4
 210 #define DSI_INT_MSK1                    0xc8
 211
 212 #define PHY_STATUS_TIMEOUT_US           10000
 213 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 214
 215 #define BYPASS_VCO_RANGE        BIT(7)
 216 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 217 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 218 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 219 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 220 #define REF_BIAS_CUR_SEL        BIT(0)
 221
 222 #define CP_CURRENT_3MA          BIT(3)
 223 #define CP_PROGRAM_EN           BIT(7)
 224 #define LPF_PROGRAM_EN          BIT(6)
 225 #define LPF_RESISTORS_20_KOHM   0
 226
 227 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 228
 229 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 230 #define LOW_PROGRAM_EN          0
 231 #define HIGH_PROGRAM_EN         BIT(7)
 232 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 233 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 234 #define PLL_LOOP_DIV_EN         BIT(5)
 235 #define PLL_INPUT_DIV_EN        BIT(4)
 236
 237 #define POWER_CONTROL           BIT(6)
 238 #define INTERNAL_REG_CURRENT    BIT(3)
 239 #define BIAS_BLOCK_ON           BIT(2)
 240 #define BANDGAP_ON              BIT(0)
 241
 242 #define TER_RESISTOR_HIGH       BIT(7)
 243 #define TER_RESISTOR_LOW        0
 244 #define LEVEL_SHIFTERS_ON       BIT(6)
 245 #define TER_CAL_DONE            BIT(5)
 246 #define SETRD_MAX               (0x7 << 2)
 247 #define POWER_MANAGE            BIT(1)
 248 #define TER_RESISTORS_ON        BIT(0)
 249
 250 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 251 #define BANDGAP_SEL(val)        ((val) & 0x7)
 252 #define TLP_PROGRAM_EN          BIT(7)
 253 #define THS_PRE_PROGRAM_EN      BIT(7)
 254 #define THS_ZERO_PROGRAM_EN     BIT(6)
 255
 256 enum {
 257         BANDGAP_97_07,
 258         BANDGAP_98_05,
 259         BANDGAP_99_02,
 260         BANDGAP_100_00,
 261         BANDGAP_93_17,
 262         BANDGAP_94_15,
 263         BANDGAP_95_12,
 264         BANDGAP_96_10,
 265 };
 266
 267 enum {
 268         BIASEXTR_87_1,
 269         BIASEXTR_91_5,
 270         BIASEXTR_95_9,
 271         BIASEXTR_100,
 272         BIASEXTR_105_94,
 273         BIASEXTR_111_88,
 274         BIASEXTR_118_8,
 275         BIASEXTR_127_7,
 276 };
 277
 278 struct dw_mipi_dsi_plat_data {
 279         u32 dsi0_en_bit;
 280         u32 dsi1_en_bit;
 281         u32 grf_switch_reg;
 282         u32 grf_dsi0_mode;
 283         u32 grf_dsi0_mode_reg;
 284         unsigned int max_data_lanes;
 285         u32 max_bit_rate_per_lane;
 286         bool has_separate_phy;
 287         bool has_phy_pclk;
 288         bool has_phy_refclk;
 289         bool has_vop_sel;
 290         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 291                                            struct drm_display_mode *mode);
 292 };
 293
 294 struct dw_mipi_dsi {
 295         struct drm_encoder encoder;
 296         struct drm_connector connector;
 297         struct mipi_dsi_host dsi_host;
 298         struct phy *phy;
 299         struct drm_panel *panel;
 300         struct device *dev;
 301         struct regmap *grf_regmap;
 302         struct reset_control *rst;
 303         void __iomem *base;
 304
 305         struct clk *pllref_clk;
 306         struct clk *pclk;
 307         struct clk *phy_cfg_clk;
 308
 309         unsigned int lane_mbps; /* per lane */
 310         u32 channel;
 311         u32 lanes;
 312         u32 format;
 313         u16 input_div;
 314         u16 feedback_div;
 315         struct drm_display_mode mode;
 316
 317         const struct dw_mipi_dsi_plat_data *pdata;
 318 };
 319
 320 enum dw_mipi_dsi_mode {
 321         DW_MIPI_DSI_CMD_MODE,
 322         DW_MIPI_DSI_VID_MODE,
 323 };
 324
 325 struct dphy_pll_testdin_map {
 326         unsigned int max_mbps;
 327         u8 testdin;
 328 };
 329
 330 /* The table is based on 27MHz DPHY pll reference clock. */
 331 static const struct dphy_pll_testdin_map dptdin_map[] = {
 332         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 333         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 334         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 335         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 336         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 337         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 338         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 339         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 340         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 341         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 342 };
 343
 344 static int max_mbps_to_testdin(unsigned int max_mbps)
 345 {
 346         int i;
 347
 348         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 349                 if (dptdin_map[i].max_mbps > max_mbps)
 350                         return dptdin_map[i].testdin;
 351
 352         return -EINVAL;
 353 }
 354
 355 /*
 356  * The controller should generate 2 frames before
 357  * preparing the peripheral.
 358  */
 359 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 360 {
 361         int refresh, two_frames;
 362
 363         refresh = drm_mode_vrefresh(&dsi->mode);
 364         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 365         msleep(two_frames);
 366 }
 367
 368 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 369 {
 370         return container_of(host, struct dw_mipi_dsi, dsi_host);
 371 }
 372
 373 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 374 {
 375         return container_of(con, struct dw_mipi_dsi, connector);
 376 }
 377
 378 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 379 {
 380         return container_of(encoder, struct dw_mipi_dsi, encoder);
 381 }
 382 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 383 {
 384         writel(val, dsi->base + reg);
 385 }
 386
 387 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 388 {
 389         return readl(dsi->base + reg);
 390 }
 391
 392 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 393                                  u8 test_data)
 394 {
 395         /*
 396          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 397          * is latched internally as the current test code. Test data is
 398          * programmed internally by rising edge on TESTCLK.
 399          */
 400         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 401
 402         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 403                                           PHY_TESTDIN(test_code));
 404
 405         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 406
 407         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 408                                           PHY_TESTDIN(test_data));
 409
 410         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 411 }
 412
 413 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 414 {
 415         int ret, testdin, vco, val;
 416
 417         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 418
 419         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 420         if (testdin < 0) {
 421                 dev_err(dsi->dev,
 422                         "failed to get testdin for %dmbps lane clock\n",
 423                         dsi->lane_mbps);
 424                 return testdin;
 425         }
 426
 427         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 428
 429         if (!IS_ERR(dsi->phy_cfg_clk)) {
 430                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 431                 if (ret) {
 432                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 433                         return ret;
 434                 }
 435         }
 436
 437         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 438                                          VCO_RANGE_CON_SEL(vco) |
 439                                          VCO_IN_CAP_CON_LOW |
 440                                          REF_BIAS_CUR_SEL);
 441
 442         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 443         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 444                                          LPF_RESISTORS_20_KOHM);
 445
 446         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 447
 448         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 449         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 450         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 451                                          LOW_PROGRAM_EN);
 452         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 453                                          HIGH_PROGRAM_EN);
 454
 455         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 456                                          BIAS_BLOCK_ON | BANDGAP_ON);
 457
 458         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 459                                          SETRD_MAX | TER_RESISTORS_ON);
 460         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 461                                          SETRD_MAX | POWER_MANAGE |
 462                                          TER_RESISTORS_ON);
 463
 464         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 465                                          BIASEXTR_SEL(BIASEXTR_127_7));
 466         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 467                                          BANDGAP_SEL(BANDGAP_96_10));
 468
 469         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 470         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 471         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 472
 473         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 474                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 475
 476
 477         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 478                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 479         if (ret < 0) {
 480                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 481                 goto phy_init_end;
 482         }
 483
 484         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 485                                  val, val & STOP_STATE_CLK_LANE, 1000,
 486                                  PHY_STATUS_TIMEOUT_US);
 487         if (ret < 0)
 488                 dev_err(dsi->dev,
 489                         "failed to wait for phy clk lane stop state\n");
 490
 491 phy_init_end:
 492         if (!IS_ERR(dsi->phy_cfg_clk))
 493                 clk_disable_unprepare(dsi->phy_cfg_clk);
 494
 495         return ret;
 496 }
 497
 498 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 499 {
 500         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 501         unsigned int i, pre;
 502         unsigned long mpclk, pllref, tmp;
 503         unsigned int m = 1, n = 1, target_mbps = 1000;
 504         unsigned int max_mbps = pdata->max_bit_rate_per_lane / USEC_PER_SEC;
 505         int bpp;
 506
 507         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 508         if (bpp < 0) {
 509                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 510                         dsi->format);
 511                 return bpp;
 512         }
 513
 514         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 515         if (mpclk) {
 516                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 517                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 518                 if (tmp < max_mbps)
 519                         target_mbps = tmp;
 520                 else
 521                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 522         }
 523
 524         if (pdata->has_phy_refclk)
 525                 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk),
 526                                       USEC_PER_SEC);
 527         else
 528                 pllref = DIV_ROUND_UP(12000000, USEC_PER_SEC);
 529
 530         tmp = pllref;
 531
 532         for (i = 1; i < 6; i++) {
 533                 pre = pllref / i;
 534                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 535                         tmp = target_mbps % pre;
 536                         n = i;
 537                         m = target_mbps / pre;
 538                 }
 539                 if (tmp == 0)
 540                         break;
 541         }
 542
 543         dsi->lane_mbps = pllref / n * m;
 544         dsi->input_div = n;
 545         dsi->feedback_div = m;
 546
 547         return 0;
 548 }
 549
 550 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 551                                    struct mipi_dsi_device *device)
 552 {
 553         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 554
 555         if (device->lanes > dsi->pdata->max_data_lanes) {
 556                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 557                                 device->lanes);
 558                 return -EINVAL;
 559         }
 560
 561         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 562                 dev_err(dsi->dev, "device mode is unsupported\n");
 563                 return -EINVAL;
 564         }
 565
 566         dsi->lanes = device->lanes;
 567         dsi->channel = device->channel;
 568         dsi->format = device->format;
 569
 570         dsi->panel = of_drm_find_panel(device->dev.of_node);
 571         if (!dsi->panel) {
 572                 DRM_ERROR("failed to find panel\n");
 573                 return -ENODEV;
 574         }
 575
 576         return 0;
 577 }
 578
 579 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 580                                    struct mipi_dsi_device *device)
 581 {
 582         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 583
 584         if (dsi->panel)
 585                 drm_panel_detach(dsi->panel);
 586
 587         dsi->panel = NULL;
 588         return 0;
 589 }
 590
 591 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 592 {
 593         int ret;
 594         int sts = 0;
 595
 596         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 597                                  sts, !(sts & GEN_CMD_FULL), 1000,
 598                                  CMD_PKT_STATUS_TIMEOUT_US);
 599
 600         if (ret < 0) {
 601                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 602                 return ret;
 603         }
 604
 605         dsi_write(dsi, DSI_GEN_HDR, val);
 606
 607         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 608                                  sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 609                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 610
 611         if (ret < 0) {
 612                 dev_err(dsi->dev, "failed to write command FIFO\n");
 613                 return ret;
 614         }
 615
 616         return 0;
 617 }
 618
 619 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
 620                                    const struct mipi_dsi_msg *msg)
 621 {
 622         const u16 *tx_buf = msg->tx_buf;
 623         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 624
 625         if (msg->tx_len > 2) {
 626                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 627                         msg->tx_len);
 628                 return -EINVAL;
 629         }
 630
 631         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 632 }
 633
 634 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
 635                                   const struct mipi_dsi_msg *msg)
 636 {
 637         const u32 *tx_buf = msg->tx_buf;
 638         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 639         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 640         u32 remainder = 0;
 641         u32 sts = 0;
 642
 643         if (msg->tx_len < 3) {
 644                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 645                         msg->tx_len);
 646                 return -EINVAL;
 647         }
 648
 649         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 650                 if (len < pld_data_bytes) {
 651                         memcpy(&remainder, tx_buf, len);
 652                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 653                         len = 0;
 654                 } else {
 655                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 656                         tx_buf++;
 657                         len -= pld_data_bytes;
 658                 }
 659
 660                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 661                                          sts, !(sts & GEN_PLD_W_FULL), 1000,
 662                                          CMD_PKT_STATUS_TIMEOUT_US);
 663                 if (ret < 0) {
 664                         dev_err(dsi->dev,
 665                                 "failed to get available write payload FIFO\n");
 666                         return ret;
 667                 }
 668         }
 669
 670         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 671 }
 672
 673 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 674                                          const struct mipi_dsi_msg *msg)
 675 {
 676         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 677         int ret;
 678
 679         switch (msg->type) {
 680         case MIPI_DSI_DCS_SHORT_WRITE:
 681         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 682         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 683         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 684         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 685         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 686                 ret = dw_mipi_dsi_short_write(dsi, msg);
 687                 break;
 688         case MIPI_DSI_DCS_LONG_WRITE:
 689         case MIPI_DSI_GENERIC_LONG_WRITE:
 690                 ret = dw_mipi_dsi_long_write(dsi, msg);
 691                 break;
 692         default:
 693                 dev_err(dsi->dev, "unsupported message type\n");
 694                 ret = -EINVAL;
 695         }
 696
 697         return ret;
 698 }
 699
 700 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 701         .attach = dw_mipi_dsi_host_attach,
 702         .detach = dw_mipi_dsi_host_detach,
 703         .transfer = dw_mipi_dsi_host_transfer,
 704 };
 705
 706 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 707 {
 708         u32 val;
 709
 710         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 711
 712         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 713 }
 714
 715 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 716                                  enum dw_mipi_dsi_mode mode)
 717 {
 718         if (mode == DW_MIPI_DSI_CMD_MODE) {
 719                 dsi_write(dsi, DSI_PWR_UP, RESET);
 720                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 721                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 722         } else {
 723                 dsi_write(dsi, DSI_PWR_UP, RESET);
 724                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 725                 dw_mipi_dsi_video_mode_config(dsi);
 726                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 727         }
 728 }
 729
 730 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 731 {
 732         dsi_write(dsi, DSI_PWR_UP, RESET);
 733         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 734 }
 735
 736 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 737 {
 738         dsi_write(dsi, DSI_PWR_UP, RESET);
 739         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 740                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 741         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 742                   TX_ESC_CLK_DIVIDSION(7));
 743         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 744 }
 745
 746 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 747                                    struct drm_display_mode *mode)
 748 {
 749         u32 val = 0, color = 0;
 750
 751         switch (dsi->format) {
 752         case MIPI_DSI_FMT_RGB888:
 753                 color = DPI_COLOR_CODING_24BIT;
 754                 break;
 755         case MIPI_DSI_FMT_RGB666:
 756                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 757                 break;
 758         case MIPI_DSI_FMT_RGB666_PACKED:
 759                 color = DPI_COLOR_CODING_18BIT_1;
 760                 break;
 761         case MIPI_DSI_FMT_RGB565:
 762                 color = DPI_COLOR_CODING_16BIT_1;
 763                 break;
 764         }
 765
 766         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 767                 val |= VSYNC_ACTIVE_LOW;
 768         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 769                 val |= HSYNC_ACTIVE_LOW;
 770
 771         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 772         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 773         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 774         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 775                   | INVACT_LPCMD_TIME(4));
 776 }
 777
 778 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 779 {
 780         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 781 }
 782
 783 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 784                                             struct drm_display_mode *mode)
 785 {
 786         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 787 }
 788
 789 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 790 {
 791         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 792         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 793         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 794         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 795 }
 796
 797 /* Get lane byte clock cycles. */
 798 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 799                                            u32 hcomponent)
 800 {
 801         u32 frac, lbcc;
 802
 803         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 804
 805         frac = lbcc % dsi->mode.clock;
 806         lbcc = lbcc / dsi->mode.clock;
 807         if (frac)
 808                 lbcc++;
 809
 810         return lbcc;
 811 }
 812
 813 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 814 {
 815         u32 htotal, hsa, hbp, lbcc;
 816         struct drm_display_mode *mode = &dsi->mode;
 817
 818         htotal = mode->htotal;
 819         hsa = mode->hsync_end - mode->hsync_start;
 820         hbp = mode->htotal - mode->hsync_end;
 821
 822         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 823         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 824
 825         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 826         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 827
 828         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 829         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 830 }
 831
 832 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 833 {
 834         u32 vactive, vsa, vfp, vbp;
 835         struct drm_display_mode *mode = &dsi->mode;
 836
 837         vactive = mode->vdisplay;
 838         vsa = mode->vsync_end - mode->vsync_start;
 839         vfp = mode->vsync_start - mode->vdisplay;
 840         vbp = mode->vtotal - mode->vsync_end;
 841
 842         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 843         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 844         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 845         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 846 }
 847
 848 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 849 {
 850         /*
 851          * HS-PREPARE: 40ns + 4 * UI ~ 85ns + 6 * UI
 852          * HS-EXIT: 100ns
 853          */
 854         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 855                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 856
 857         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 858                   | PHY_CLKLP2HS_TIME(0x40));
 859 }
 860
 861 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 862 {
 863         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 864                   N_LANES(dsi->lanes));
 865 }
 866
 867 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 868 {
 869         dsi_read(dsi, DSI_INT_ST0);
 870         dsi_read(dsi, DSI_INT_ST1);
 871         dsi_write(dsi, DSI_INT_MSK0, 0);
 872         dsi_write(dsi, DSI_INT_MSK1, 0);
 873 }
 874
 875 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 876                                         struct drm_display_mode *mode,
 877                                         struct drm_display_mode *adjusted_mode)
 878 {
 879         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 880
 881         drm_mode_copy(&dsi->mode, adjusted_mode);
 882 }
 883
 884 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 885 {
 886         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 887
 888         drm_panel_disable(dsi->panel);
 889
 890         if (clk_prepare_enable(dsi->pclk)) {
 891                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 892                 return;
 893         }
 894
 895         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 896         drm_panel_unprepare(dsi->panel);
 897         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 898
 899         /*
 900          * This is necessary to make sure the peripheral will be driven
 901          * normally when the display is enabled again later.
 902          */
 903         msleep(120);
 904
 905         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 906         dw_mipi_dsi_disable(dsi);
 907         phy_power_off(dsi->phy);
 908         pm_runtime_put(dsi->dev);
 909         clk_disable_unprepare(dsi->pclk);
 910 }
 911
 912 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 913                                         const struct drm_display_mode *mode,
 914                                         struct drm_display_mode *adjusted_mode)
 915 {
 916         return true;
 917 }
 918
 919 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 920 {
 921         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 922         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 923         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 924         int ret;
 925         u32 val;
 926
 927         if (clk_prepare_enable(dsi->pclk)) {
 928                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 929                 return;
 930         }
 931
 932         if (dsi->rst) {
 933                 /* MIPI DSI APB software reset request. */
 934                 reset_control_assert(dsi->rst);
 935                 udelay(10);
 936                 reset_control_deassert(dsi->rst);
 937                 udelay(10);
 938         }
 939
 940         ret = dw_mipi_dsi_get_lane_bps(dsi);
 941         if (ret < 0)
 942                 return;
 943
 944         pm_runtime_get_sync(dsi->dev);
 945
 946         phy_power_on(dsi->phy);
 947         dw_mipi_dsi_init(dsi);
 948         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 949         dw_mipi_dsi_packet_handler_config(dsi);
 950         dw_mipi_dsi_video_mode_config(dsi);
 951         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 952         dw_mipi_dsi_command_mode_config(dsi);
 953         dw_mipi_dsi_line_timer_config(dsi);
 954         dw_mipi_dsi_vertical_timing_config(dsi);
 955         dw_mipi_dsi_dphy_timing_config(dsi);
 956         dw_mipi_dsi_dphy_interface_config(dsi);
 957         dw_mipi_dsi_clear_err(dsi);
 958         if (drm_panel_prepare(dsi->panel))
 959                 dev_err(dsi->dev, "failed to prepare panel\n");
 960
 961         if (pdata->grf_dsi0_mode_reg)
 962                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 963                              pdata->grf_dsi0_mode);
 964
 965         dw_mipi_dsi_phy_init(dsi);
 966         dw_mipi_dsi_wait_for_two_frames(dsi);
 967
 968         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 969         drm_panel_enable(dsi->panel);
 970
 971         clk_disable_unprepare(dsi->pclk);
 972
 973         if (!pdata->has_vop_sel)
 974                 return;
 975
 976         if (mux)
 977                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 978         else
 979                 val = pdata->dsi0_en_bit << 16;
 980
 981         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 982         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 983 }
 984
 985 static int
 986 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 987                                  struct drm_crtc_state *crtc_state,
 988                                  struct drm_connector_state *conn_state)
 989 {
 990         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 991         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 992         struct drm_connector *connector = conn_state->connector;
 993         struct drm_display_info *info = &connector->display_info;
 994
 995         switch (dsi->format) {
 996         case MIPI_DSI_FMT_RGB888:
 997                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 998                 break;
 999         case MIPI_DSI_FMT_RGB666:
1000                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1001                 break;
1002         case MIPI_DSI_FMT_RGB565:
1003                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1004                 break;
1005         default:
1006                 WARN_ON(1);
1007                 return -EINVAL;
1008         }
1009
1010         s->output_type = DRM_MODE_CONNECTOR_DSI;
1011         if (info->num_bus_formats)
1012                 s->bus_format = info->bus_formats[0];
1013
1014         return 0;
1015 }
1016
1017 static struct drm_encoder_helper_funcs
1018 dw_mipi_dsi_encoder_helper_funcs = {
1019         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1020         .mode_set = dw_mipi_dsi_encoder_mode_set,
1021         .enable = dw_mipi_dsi_encoder_enable,
1022         .disable = dw_mipi_dsi_encoder_disable,
1023         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1024 };
1025
1026 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1027         .destroy = drm_encoder_cleanup,
1028 };
1029
1030 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1031 {
1032         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1033
1034         return drm_panel_get_modes(dsi->panel);
1035 }
1036
1037 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1038                                         struct drm_connector *connector,
1039                                         struct drm_display_mode *mode)
1040 {
1041         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1042
1043         enum drm_mode_status mode_status = MODE_OK;
1044
1045         if (dsi->pdata->mode_valid)
1046                 mode_status = dsi->pdata->mode_valid(connector, mode);
1047
1048         return mode_status;
1049 }
1050
1051 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1052                                         struct drm_connector *connector)
1053 {
1054         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1055
1056         return &dsi->encoder;
1057 }
1058
1059 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1060 {
1061         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1062
1063         if (on)
1064                 pm_runtime_get_sync(dsi->dev);
1065         else
1066                 pm_runtime_put(dsi->dev);
1067
1068         return 0;
1069 }
1070
1071 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1072         .loader_protect = dw_mipi_loader_protect,
1073         .get_modes = dw_mipi_dsi_connector_get_modes,
1074         .mode_valid = dw_mipi_dsi_mode_valid,
1075         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1076 };
1077
1078 static enum drm_connector_status
1079 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1080 {
1081         return connector_status_connected;
1082 }
1083
1084 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1085 {
1086         drm_connector_unregister(connector);
1087         drm_connector_cleanup(connector);
1088 }
1089
1090 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1091         .dpms = drm_atomic_helper_connector_dpms,
1092         .fill_modes = drm_helper_probe_single_connector_modes,
1093         .detect = dw_mipi_dsi_detect,
1094         .destroy = dw_mipi_dsi_drm_connector_destroy,
1095         .reset = drm_atomic_helper_connector_reset,
1096         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1097         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1098 };
1099
1100 static int dw_mipi_dsi_register(struct drm_device *drm,
1101                                       struct dw_mipi_dsi *dsi)
1102 {
1103         struct drm_encoder *encoder = &dsi->encoder;
1104         struct drm_connector *connector = &dsi->connector;
1105         struct device *dev = dsi->dev;
1106         int ret;
1107
1108         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1109                                                              dev->of_node);
1110         /*
1111          * If we failed to find the CRTC(s) which this encoder is
1112          * supposed to be connected to, it's because the CRTC has
1113          * not been registered yet.  Defer probing, and hope that
1114          * the required CRTC is added later.
1115          */
1116         if (encoder->possible_crtcs == 0)
1117                 return -EPROBE_DEFER;
1118
1119         drm_encoder_helper_add(&dsi->encoder,
1120                                &dw_mipi_dsi_encoder_helper_funcs);
1121         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1122                          DRM_MODE_ENCODER_DSI, NULL);
1123         if (ret) {
1124                 dev_err(dev, "Failed to initialize encoder with drm\n");
1125                 return ret;
1126         }
1127
1128         drm_connector_helper_add(connector,
1129                         &dw_mipi_dsi_connector_helper_funcs);
1130
1131         drm_connector_init(drm, &dsi->connector,
1132                            &dw_mipi_dsi_atomic_connector_funcs,
1133                            DRM_MODE_CONNECTOR_DSI);
1134
1135         drm_panel_attach(dsi->panel, &dsi->connector);
1136
1137         dsi->connector.port = dev->of_node;
1138
1139         drm_mode_connector_attach_encoder(connector, encoder);
1140
1141         return 0;
1142 }
1143
1144 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1145 {
1146         struct device_node *np = dsi->dev->of_node;
1147
1148         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1149         if (IS_ERR(dsi->grf_regmap)) {
1150                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1151                 return PTR_ERR(dsi->grf_regmap);
1152         }
1153
1154         return 0;
1155 }
1156
1157 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1158         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1159         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1160         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1161         .max_data_lanes = 4,
1162         .max_bit_rate_per_lane = 1500000000,
1163         .has_vop_sel = true,
1164         .has_phy_refclk = true,
1165         .has_phy_pclk = true,
1166 };
1167
1168 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1169         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1170         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1171         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1172         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1173         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1174         .max_data_lanes = 4,
1175         .max_bit_rate_per_lane = 1500000000,
1176         .has_vop_sel = true,
1177         .has_phy_refclk = true,
1178         .has_phy_pclk = true,
1179 };
1180
1181 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1182         .max_data_lanes = 4,
1183         .max_bit_rate_per_lane = 1000000000,
1184         .has_separate_phy = true,
1185 };
1186
1187 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1188         {
1189          .compatible = "rockchip,rk3288-mipi-dsi",
1190          .data = &rk3288_mipi_dsi_drv_data,
1191         },{
1192          .compatible = "rockchip,rk3399-mipi-dsi",
1193          .data = &rk3399_mipi_dsi_drv_data,
1194         }, {
1195          .compatible = "rockchip,rk3368-mipi-dsi",
1196          .data = &rk3368_mipi_dsi_drv_data,
1197         },
1198         { /* sentinel */ }
1199 };
1200 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1201
1202 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1203                              void *data)
1204 {
1205         struct platform_device *pdev = to_platform_device(dev);
1206         struct drm_device *drm = data;
1207         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1208         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
1209         struct resource *res;
1210         int ret;
1211
1212         if (!dsi->panel)
1213                 return -EPROBE_DEFER;
1214
1215         ret = rockchip_mipi_parse_dt(dsi);
1216         if (ret)
1217                 return ret;
1218
1219         if (pdata->has_separate_phy) {
1220                 dsi->phy = devm_phy_get(dev, "mipi_dphy");
1221                 if (IS_ERR(dsi->phy)) {
1222                         dev_err(dev, "failed to get mipi dphy\n");
1223                         return PTR_ERR(dsi->phy);
1224                 }
1225         }
1226
1227         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228         if (!res)
1229                 return -ENODEV;
1230
1231         dsi->base = devm_ioremap_resource(dev, res);
1232         if (IS_ERR(dsi->base))
1233                 return PTR_ERR(dsi->base);
1234
1235         dsi->pclk = devm_clk_get(dev, "pclk");
1236         if (IS_ERR(dsi->pclk)) {
1237                 ret = PTR_ERR(dsi->pclk);
1238                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1239                 return ret;
1240         }
1241
1242         if (pdata->has_phy_refclk) {
1243                 dsi->pllref_clk = devm_clk_get(dev, "ref");
1244                 if (IS_ERR(dsi->pllref_clk)) {
1245                         ret = PTR_ERR(dsi->pllref_clk);
1246                         dev_err(dev, "failed to get pll ref clock: %d\n", ret);
1247                         return ret;
1248                 }
1249         }
1250
1251         if (pdata->has_phy_pclk) {
1252                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1253                 if (IS_ERR(dsi->phy_cfg_clk))
1254                         dev_dbg(dev, "have not phy_cfg_clk\n");
1255         }
1256
1257         ret = clk_prepare_enable(dsi->pllref_clk);
1258         if (ret) {
1259                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1260                 return ret;
1261         }
1262
1263         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1264         if (IS_ERR(dsi->rst)) {
1265                 dev_info(dev, "no reset control specified\n");
1266                 dsi->rst = NULL;
1267         }
1268
1269         ret = dw_mipi_dsi_register(drm, dsi);
1270         if (ret) {
1271                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1272                 goto err_pllref;
1273         }
1274
1275         dev_set_drvdata(dev, dsi);
1276
1277         pm_runtime_enable(dev);
1278
1279         return 0;
1280
1281 err_pllref:
1282         clk_disable_unprepare(dsi->pllref_clk);
1283         return ret;
1284 }
1285
1286 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1287         void *data)
1288 {
1289         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1290
1291         pm_runtime_disable(dev);
1292         clk_disable_unprepare(dsi->pllref_clk);
1293 }
1294
1295 static const struct component_ops dw_mipi_dsi_ops = {
1296         .bind   = dw_mipi_dsi_bind,
1297         .unbind = dw_mipi_dsi_unbind,
1298 };
1299
1300 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1301 {
1302         struct device *dev = &pdev->dev;
1303         const struct of_device_id *of_id =
1304                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1305         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1306         struct dw_mipi_dsi *dsi;
1307         int ret;
1308
1309         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1310         if (!dsi)
1311                 return -ENOMEM;
1312
1313         dsi->dev = dev;
1314         dsi->pdata = pdata;
1315         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1316         dsi->dsi_host.dev = &pdev->dev;
1317
1318         ret = mipi_dsi_host_register(&dsi->dsi_host);
1319         if (ret)
1320                 return ret;
1321
1322         platform_set_drvdata(pdev, dsi);
1323         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1324         if (ret)
1325                 mipi_dsi_host_unregister(&dsi->dsi_host);
1326
1327         return ret;
1328 }
1329
1330 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1331 {
1332         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1333
1334         if (dsi)
1335                 mipi_dsi_host_unregister(&dsi->dsi_host);
1336         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1337         return 0;
1338 }
1339
1340 static struct platform_driver dw_mipi_dsi_driver = {
1341         .probe          = dw_mipi_dsi_probe,
1342         .remove         = dw_mipi_dsi_remove,
1343         .driver         = {
1344                 .of_match_table = dw_mipi_dsi_dt_ids,
1345                 .name   = DRIVER_NAME,
1346         },
1347 };
1348 module_platform_driver(dw_mipi_dsi_driver);
1349
1350 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1351 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1352 MODULE_LICENSE("GPL");
1353 MODULE_ALIAS("platform:" DRIVER_NAME);