clk: rockchip: fix up the pll-type for rk3328

fix up the pll type pll_rk3328 description and use.
add the other parts handling parents,like num_parents check
and the init.num_parents parameter.
add ctx->grf.

Change-Id: I17f1b0dc4b8286817f587e02fdea39f2d886f3d0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index d26a5119ade55fa7151839804ecb0228b4749348..978c1bb86c353a0d50a0b4c5fb390ac2d72fa9b2 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1234,7 +1234,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
        struct clk *pll_clk, *mux_clk;
        char pll_name[20];
 
-       if (num_parents != 2) {
+       if ((pll_type != pll_rk3328 && num_parents != 2) ||
+           (pll_type == pll_rk3328 && num_parents != 1)) {
                pr_err("%s: needs two parent clocks\n", __func__);
                return ERR_PTR(-EINVAL);
        }
@@ -1275,7 +1276,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
        init.flags = CLK_SET_RATE_PARENT;
        init.ops = pll->pll_mux_ops;
        init.parent_names = pll_parents;
-       init.num_parents = ARRAY_SIZE(pll_parents);
+       if (pll_type == pll_rk3328)
+               init.num_parents = 2;
+       else
+               init.num_parents = ARRAY_SIZE(pll_parents);
 
        mux_clk = clk_register(NULL, &pll_mux->hw);
        if (IS_ERR(mux_clk))
@@ -1309,6 +1313,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 
        switch (pll_type) {
        case pll_rk3036:
+       case pll_rk3328:
                if (!pll->rate_table)
                        init.ops = &rockchip_rk3036_pll_clk_norate_ops;
                else
@@ -1320,12 +1325,6 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
                else
                        init.ops = &rockchip_rk3066_pll_clk_ops;
                break;
-       case pll_rk3328:
-               if (!pll->rate_table)
-                       init.ops = &rockchip_rk3036_pll_clk_norate_ops;
-               else
-                       init.ops = &rockchip_rk3036_pll_clk_ops;
-               break;
        case pll_rk3366:
                if (!pll->rate_table)
                        init.ops = &rockchip_rk3366_pll_clk_norate_ops;

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index f3d69aaa24aafb38300ef2add1e394aa143aac62..e96a2e18786250bcb30bfc9ad6b54b38d9395f17 100644 (file)
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -348,6 +348,8 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
        ctx->cru_node = np;
        ctx->grf = ERR_PTR(-EPROBE_DEFER);
        spin_lock_init(&ctx->lock);
+       ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+                                                  "rockchip,grf");
 
        return ctx;