clk: rockchip: rk3368: use the clock IDs for DPHY clocks

The DPHY(DSI PHY) in Rockchip rk3368 supports MIPI/TTL/LVDS
mode. Use the clock IDs (PCLK_DPHYRX and PCLK_DPHYTX0) for
DPHY clocks.

Change-Id: I6a133d6da839d6545e507f38b361b3457e5ff3ee
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 1e6cb17a048ca8eb520d970b2f8c8e8c61355009..096a74f97c5315905cb5f36f5cd21722ad615fb7 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -792,8 +792,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
         * pclk_vio gates
         * pclk_vio comes from the exactly same source as hclk_vio
         */
-       GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
-       GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+       GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
+       GATE(PCLK_DPHYTX0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
 
        /* pclk_pd_pmu gates */
        GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),