ARM: dts: rk3288: use operating-points-v2

Change-Id: I3cb938fbfaf0ae5957d4832f4ad5671ab9631409
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 1782db41b42fd951ea574260cfd581ac58d73cf8..d5fe9a5dd305134fab6ab4c3f681846f5e1ca7ac 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -95,23 +95,8 @@
                        compatible = "arm,cortex-a12";
                        reg = <0x500>;
                        resets = <&cru SRST_CORE0>;
-                       operating-points = <
-                               /* KHz    uV */
-                               1608000 1350000
-                               1512000 1300000
-                               1416000 1200000
-                               1200000 1100000
-                               1008000 1050000
-                                816000 1000000
-                                696000  950000
-                                600000  900000
-                                408000  900000
-                                312000  900000
-                                216000  900000
-                                126000  900000
-                       >;
+                       operating-points-v2 = <&cpu0_opp_table>;
                        #cooling-cells = <2>; /* min followed by max */
-                       clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
                };
                cpu1: cpu@501 {
@@ -119,18 +104,83 @@
                        compatible = "arm,cortex-a12";
                        reg = <0x501>;
                        resets = <&cru SRST_CORE1>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
                cpu2: cpu@502 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x502>;
                        resets = <&cru SRST_CORE2>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
                cpu3: cpu@503 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x503>;
                        resets = <&cru SRST_CORE3>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+       };
+
+       cpu0_opp_table: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp@126000000 {
+                       opp-hz = /bits/ 64 <126000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@216000000 {
+                       opp-hz = /bits/ 64 <216000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@408000000 {
+                       opp-hz = /bits/ 64 <408000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@696000000 {
+                       opp-hz = /bits/ 64 <696000000>;
+                       opp-microvolt = <950000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@816000000 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <40000>;
+                       opp-suspend;
+               };
+               opp@1008000000 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1050000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@1416000000 {
+                       opp-hz = /bits/ 64 <1296000000>;
+                       opp-microvolt = <1200000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@1512000000 {
+                       opp-hz = /bits/ 64 <1512000000>;
+                       opp-microvolt = <1300000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp@1608000000 {
+                       opp-hz = /bits/ 64 <1608000000>;
+                       opp-microvolt = <1350000>;
+                       clock-latency-ns = <40000>;
                };
        };